SOURCE: Antares Advanced Test Technologies

November 08, 2007 15:12 ET

IC Test Engineers to Consider the Effects of Package Pin Map On Signal Integrity During IMAPS Presentation by Antares Advanced Test Technologies

Antares to Discuss Nuances of Back-End Signal Integrity, Showcase Latest BGA Burn-In Technology at Leading Microelectronics and Packaging Show, Booth No. 1130

SANTA CLARA, CA and VANCOUVER, WA--(Marketwire - November 8, 2007) - Antares Advanced Test Technologies, a global supplier of integrated semiconductor-test consumables focused on maximizing chipmakers' production yields, announced today that Hongjun Yao, signal integrity manager, will deliver a presentation titled "The Effect of Package Pin Map On Signal Integrity for Test Applications" at IMAPS 2007 at the McEnery Convention Center in San Jose, Calif., next Wednesday, Nov. 14 at 3:35 p.m. PT.

Yao's signal-integrity presentation will generally discuss case studies that detail how incorporating test sockets in the package design workflow aids the signal-integrity analysis needed to deliver signals, with minimal distortions, from chip to PCB for high-speed products and ensure whole system level success.

Yao will detail how chipmakers that incorporate test sockets in package design -- including signal/ground-pin map arrangements -- and the signal-integrity equation can avoid employing more expensive high-bandwidth sockets to test their high-speed products.

"You simply can't achieve true signal integrity without taking a close look at the socket and its relationship to the package," said Dr. James Forster, Ph.D., Antares' CTO and the presentation's co-author. "And high-bandwidth sockets aren't always the solution for testing high-speed ICs -- particularly when you consider the low first-pass yield and maintenance that often characterize them."

Yao's presentation, also co-authored by Antares' James Zhou, senior staff engineer, will be delivered in Room J3, WP4 at the convention center and is open to all IMAPS 2007 attendees.

The Antares team at IMAPS 2007 will talk with attendees about the nuances of signal integrity during semiconductor test, as well as the relationship between burn-in socket technology, PCB layout and reducing board costs.

Antares will also feature the following products from its integrated semiconductor test portfolio at IMAPS 2007 at booth No. 1130 from Nov. 13-15:

Burn-in Sockets:

-  773 Series - 0.4mm pitch compression mount, CSP socket
-  774 Series - large array 0.5mm pitch, compression mount CSP socket
-  880 Series - Clamshell, compression mount 0.4mm pitch QFN
-  881 Series - Clamshell, compression mount, multi-row QFN socket

Test Sockets:

-  Kalypso - high performance test socket and contactors
-  Spring Probe - high performance test socket and contactors

Thermal Management Solutions:

-  Thermal Control Units - thermal management for test applications
-  iSocket - thermal management for burn-in

For more information on Antares' product portfolio, visit

IMAPS 2007, The 40th Annual Symposium on Microelectronics, runs from Nov. 11-15 and is the largest symposium related to the microelectronics industry and the electronic packaging industry in the world. For more information, visit

About Antares Advanced Test Technologies

Antares Advanced Test Technologies is reducing the cost of semiconductor test by concentrating on high-sensitivity areas such as yield and the integration of test disciplines, focusing on customer support, delivering innovative technologies and offering a single point of contact for semiconductor test cell requirements, including burn-in sockets, test sockets, ATE consumables and thermal management solutions. Antares is headquartered in Vancouver, Wash. and has design, development and manufacturing locations in Suzhou, China; Yokohama, Japan; Phoenix and Gilbert, Ariz.; Milpitas and Santa Clara, Calif.; and Aman, Jordan.

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