SOURCE: Lattice Semiconductor Corporation

Lattice Semiconductor Corporation

November 23, 2009 03:01 ET

Lattice Announces First Low Cost FPGA With Serial RapidIO 2.1 Support

Lowest Cost, Lowest Power Programmable SRIO Solution in the Industry

HILLSBORO, OR--(Marketwire - November 23, 2009) - Lattice Semiconductor Corporation (NASDAQ: LSCC) and Praesum Communications today announced the availability of the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3™ FPGA family. The core supports 1x, 2x and 4x lane configurations at up to 3.125Gbps lane speeds, offering the lowest cost, lowest power programmable SRIO solution in the industry. Lattice also announced that it has licensed this IP core from Praesum and has full rights to use and sub-license the Serial RapidIO IP core.

RapidIO has won broad acceptance in wireless infrastructure applications, where it is used as a primary interconnect for DSP clusters in baseband processing. In the past, vendors had to rely on expensive, premium FPGAs for these applications. However, the combination of the Serial RapidIO 2.1 core and the LatticeECP3 FPGA will now allow customers to develop low-power infrastructure solutions for 3G, LTE and WiMAX without sacrificing performance or cost. The Serial RapidIO 2.1 core and other Lattice IP cores such as low latency CPRI and GbE/SGMII comprise a comprehensive IP suite in support of wireless infrastructure applications.

"We are pleased to have been selected to provide RapidIO 2.1 endpoint IP for the Lattice low cost ECP3 FPGA. As the only supplier of fully compliant RapidIO 2.1 IP, Praesum's partnership with Lattice will help to accelerate deployment of this next generation technology in high performance signal processing applications. When combined with our RapidIO 2.1 switching IP, the endpoint IP for the LatticeECP3 FPGA represents a complete solution for wireless infrastructure equipment vendors," said Kent Dahlgren, Praesum's CEO.

"Our partnership with Praesum has yielded the first programmable Serial RapidIO 2.1 endpoint solution, and an interoperability ecosystem that will dramatically reduce cost and power for wireless infrastructure manufacturers," said Shakeel Peera, Lattice's Director of Marketing for SRAM FPGAs.

About the Serial RapidIO 2.1 IP core

Praesum is a leader in RapidIO switching, bridging, and endpoint IP. Its small footprint Serial RapidIO 2.1 IP core can be used for processor bridging, control plane interfaces and bridging to legacy interfaces. The core architecture for the Serial RapidIO 2.1 IP core includes the following features:

--  Allows for 1x, 2x, 4x lane configurations
--  Up to 3.125Gbps
--  Implements physical layer, transport layer, maintenance transaction
    handling and error management extensions
--  Provides infrastructure support for external logical layer functions,
    enabling maximum flexibility
--  Provides a choice of logical layer functions that are important for
    the application
--  Provides a choice of how logic layer functions interact with the rest
    of the system -- SOC bus or streaming interfaces
--  Supports software implementations of control plane oriented functions
    such as doorbells and messages
--  Backward compatible with the v1.3 specification

For additional information about the Serial RapidIO 2.1 IP core, please visit

About the LatticeECP3 FPGA Family

The LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline applications.

Pricing and Availability

The Serial RapidIO 2.1 IP core is available for immediate customer evaluation and use. For more information about licensing and pricing of the Serial RapidIO 2.1 core, please contact your local Lattice sales office.

About Praesum Communications

Praesum Communications develops and deploys smart switching technologies in the form of IP cores, boards and system level products. Praesum was founded in January 2000 and has its headquarters in Petaluma, Calif. For more information, visit the Praesum web site at

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit

Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP3 and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Contact Information

    Brian Kiernan
    Corporate Communications Manager
    Lattice Semiconductor Corporation
    503-268-8739 voice
    503-268-8193 fax