SOURCE: Lattice Semiconductor Corporation

April 28, 2008 08:00 ET

Lattice Announces New CPLD Family for Low Power, High Volume Portable Applications

ispMACH 4000ZE CPLDs Address Increasing Demand for Small, Low Power and Low Cost Portable Products

HILLSBORO, OR--(Marketwire - April 28, 2008) - Lattice Semiconductor (NASDAQ: LSCC) today announced its new, ultra low power Complex Programmable Logic Devices (CPLD), the 1.8-volt ispMACH® 4000ZE family. This second-generation in-system programmable CPLD family is ideal for low power, high volume portable applications, with typical standby current as low as 10µA. The cost optimized and feature rich ispMACH 4000ZE devices offer ultra-small, space saving chip scale Ball Grid Array (csBGA) package options, a new Power Guard feature that provides ultra-low system power, and new system integration capabilities, including an on-chip user oscillator and timer. The ispMACH 4000ZE family will be offered in four logic densities, from 32 to 256 macrocells. Samples of the first two devices, the 32-macrocell ispMACH 4032ZE and the 64-macrocell ispMACH 4064ZE, are available now.

"With its low standby current, small form factor and 'instant-on' operation, the ispMACH 4000ZE family is ideal for handheld and portable equipment such as GPS systems, portable media players and wireless appliances," said Stan Kopec, Lattice corporate vice president of marketing. "With over 15 years of experience in the CPLD market, Lattice is uniquely positioned to deliver a product family that serves these emerging applications."

New System Features

The ispMACH 4000ZE family offers enhanced system features such as Power Guard dynamic power reduction; per pin pull-up, pull-down or bus keeper control; an on-chip user oscillator and timer; and input hysteresis. The Power Guard feature lowers power consumption by selectively disabling unused input pins so their switching does not consume dynamic power needlessly. This feature consists of an enabling multiplexer between the I/O pin and the input buffer and its associated circuitry inside the device. All I/O pins in a block share a common Block Input Enable (BIE) signal. Depending on the device size, there can be from 2 to 16 blocks per device. Any I/O pin in the block can be programmed to ignore the BIE signal, allowing the Power Guard feature to be enabled or disabled on a pin-by-pin basis.

An internal oscillator also is provided for use in miscellaneous housekeeping functions such as watchdog "heartbeat" functions, digital de-glitch circuits and control state machines. The ispMACH 4000ZE family also offers "always on" input hysteresis for each pin. This new feature provides improved noise immunity for 3.3V and 2.5V inputs.

Ultra-Small Space Saving Packages

The ispMACH 4000ZE family is available in space saving 0.5-millimeter ball pitch 64-ball and 144-ball csBGA packages. These small PCB-footprint packages, five millimeters square and seven millimeters square, respectively, satisfy the tight space constraints often found with portable and handheld equipment. The ispMACH 4000ZE family also is offered in more traditional 48-pin, 100-pin and 144-pin TQFP packages, and supports system designers' need for density migration within a common package/pinout footprint across multiple device densities. The ispMACH 4000ZE devices are also pin-compatible with Lattice's earlier ispMACH 4000Z devices in corresponding packages. All ispMACH 4000ZE family package options are Pb-free and RoHS compliant.

Power Supply and I/O Standard Support

The ispMACH 4000ZE devices operate from a nominal 1.8-volt power supply with operation extended down to 1.6-volts, accommodating extended end-of-battery-life voltages that can provide useful added margin for many systems. The ispMACH 4000ZE devices have two I/O banks, each with its own power supply voltage that can be set at the appropriate level to support LVTTL and LVCMOS 3.3, 2.5, 1.8 and 1.5-volt outputs. The device input buffers have programmable thresholds that support the above standards independent of the I/O bank voltage. Extended range 3.3-volt I/O current is supported, instead of the more common narrow range version. The I/Os on the ispMACH 4000ZE devices are 5-volt tolerant to facilitate connection to legacy chips and interfaces. All ispMACH 4000ZE devices are Boundary Scan Testable and in-system programmable through an IEEE 1532-compliant JTAG boundary scan (IEEE 1149.1) interface.

Design Tools

The ispMACH 4000ZE family is supported by Lattice's ispLEVER® Classic design tool suite. The ispLEVER Classic design software is a comprehensive programmable logic design environment. It includes a powerful suite of tools supporting all design tasks, including project management, HDL design entry, module/IP integration, place and route, timing analysis, programming and much more. The ispLEVER Classic design software includes all the features necessary to take a project from concept to programmed device.

Pricing and Availability

The ispMACH 4032ZE CPLD is available in the 48-TQFP and 64-ball csBGA package. The ispMACH 4064ZE CPLD is available in the 48-TQFP, 64-ball csBGA, 100-TQFP and 144-ball csBGA. Both devices are sampling now and are available in both commercial and industrial temperature options. The entire ispMACH 4000ZE family is expected to be released mid-2008. Projected pricing for the ispMACH 4032ZE is less than $.70 in 100,000 piece quantities, and for the ispMACH 4064ZE less than $.85 in 100,000 piece quantities.

About Lattice Semiconductor

Lattice Semiconductor Corporation provides the industry's broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products.

Lattice continues to deliver "More of the Best" to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. For more information, visit

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our third party silicon suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispMACH, ispLEVER and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Contact Information

    Brian Kiernan
    Corporate Communications Manager
    Lattice Semiconductor Corporation
    503-268-8739 voice
    503-268-8193 fax