SOURCE: Lattice Semiconductor Corporation

Lattice Semiconductor Corporation

November 16, 2009 03:01 ET

LatticeECP3 FPGA Family Wins Prestigious e-Legacy Awards Competition

Lowest Power SERDES FPGA Family Recognized for "Best Environmental Design"

HILLSBORO, OR--(Marketwire - November 16, 2009) - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that its mid-range, low power LatticeECP3™ FPGA family has won the highly regarded e-Legacy Awards competition sponsored by Electronic Product Design magazine. Lattice was honored in the coveted Environmental Design category, and was the only programmable logic company to be named a finalist in any of the competition's award categories.

"While power saving is a key driver for electronics designers, the judges were impressed that the LatticeECP3 FPGA could also deliver upfront cost-savings," said Tim Fryer, managing editor of Electronic Product Design magazine. "In some cases, the ECP3 device's environmental benefit might be secondary to low cost, while in the majority of projects the ECP3 device's low power would be a prime consideration."

The Environmental Design award recognizes an electronic design that is environmentally sensitive due to its energy saving and power efficiency. Finalists were chosen by a panel of industry experts, and the winners were selected by the readers of Electronic Product Design magazine. "It is the combination of expert judges and the public vote that gives the e-Legacy Awards their credence, so both finalists and eventual winners have much to be proud of," said Fryer. Winners were announced at the e-Legacy Awards luncheon at the Roof Gardens in Kensington, London on Wednesday, November 4th.

"We are honored to receive this award for our ECP3 FPGA family," said Sean Riley, Lattice Corporate Vice President and General Manager of High Density Solutions. "Low power is a priority for systems with tight operating budgets as well as an environmental responsibility for the companies that deploy them. It seems almost daily that new and conflicting claims and counterclaims are made for low power FPGAs, and so it is very gratifying that our ECP3 FPGA family has been recognized for its low power by independent judges and voters. Power definitely does matter, and our ECP3 FPGA family was designed from the bottom up to be the lowest power SERDES-capable device in the industry, without sacrificing the benefits of high speed serial I/O and processing capabilities."

About the LatticeECP3 FPGA Family

The LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The LatticeECP3 FPGA family's high performance features include:

--  3.2Gbps SERDES with 10GbE XAUI jitter compliance and the ability to
    mix and match multiple protocols on each SERDES quad. This includes PCI
    Express, CPRI, OBSAI, XAUI, Serial RapidIO and SGMII/Gigabit Ethernet.
--  The SERDES/PCS blocks have been designed specifically to enable the
    design of the low latency variation CPRI links that are found in wireless
    basestations with Remote Radio Head connectivity.
--  Compliance to the SMPTE Serial Digital Interface standard, with the
    unprecedented ability to support 3G, HD and SD video broadcast signals
    independently on each SERDES channel. The triple rate support is performed
    without any oversampling technique, consuming the least possible amount of
--  DSP blocks allowing up to 36x36 Multiply and Accumulate functions
    running at greater than 400MHz. The DSP slices also feature innovative
    cascadability for implementing wide ALU and adder tree functions without
    the performance bottlenecks of FPGA logic.
--  1Gbps LVDS I/O, with Input Delay blocks, allows interfacing to high
    performance ADCs and DACs.

With these features, the LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging, applications. For more information about the LatticeECP3 FPGA family, visit

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit

Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP3 and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Contact Information

    Brian Kiernan
    Corporate Communications Manager
    Lattice Semiconductor Corporation
    503-268-8739 voice
    503-268-8193 fax