SOURCE: Real Intent

Real Intent, formal verification, EDA, Electronic Design Automation, ASIC, FPGA

February 02, 2010 20:28 ET

Real Intent Focuses on Proven, Cost-Effective Electronic Design Verification at DVCon

Exhibit Features Demonstrations of Newest Products

SAN JOSE, CA--(Marketwire - February 2, 2010) -


Real Intent, Inc., the innovator in automating the intelligence of formal technologies for electronic design verification, is exhibiting at the 2010 Design Verification Conference (DVCon) in San Jose, California.

Real Intent's DVCon exhibit features demonstrations of proven, cost-effective automatic verification solutions, including:

-- Ascent™, for automatic, early functional verification;

-- Meridian™, for comprehensive and precise Clock Domain Crossing (CDC) verification;

-- PureTime™, for comprehensive design constraint validation, including glitch-aware timing exceptions verification.


2:00 - 6:30pm, Tuesday, February 23 and Wednesday, February 24

Bayshore Ballroom, Booth 602, DoubleTree Hotel, San Jose, California

Information and Registration

To schedule a DVCon meeting or demonstration, please email

For more information about Real Intent and its verification product families, please visit

To register for DVCon, please visit

About Real Intent

Real Intent is the innovator in automating the intelligence of formal techniques for design verification. This technology is being used to solve critical problems encountered by electronic design and verification teams worldwide. Real Intent's family of products dramatically improves the functional verification efficiency of leading edge ASIC and FPGA devices.

Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: +1 (408) 830-0700 fax: +1 (408) 737-1962, Web:, e-mail:, Twitter:

Ascent, Meridian, and PureTime are trademarks of Real Intent, Inc.

All other trademarks and trade names are the property of their respective owners.

Contact Information