SOURCE: Real Intent

June 04, 2007 09:00 ET

Reminder - Real Intent Invites Design Automation Conference Attendees to Experience Life at the Beach and Complete Timing Closure Verification for Design Sign-Off

DAC Booth 5260, June 4-7, San Diego, California

SAN DIEGO, CA--(Marketwire - June 4, 2007) -


Real Intent, the leading supplier of formal verification software for electronic design, is demonstrating its newest formal verification software at the 44th Design Automation Conference (DAC), and inviting attendees to stop by and experience life at the beach in their booth, as well as complete Timing Closure Verification (TCV) for sign-off.


Real Intent is demonstrating its newest product, EnVision TCV, the only complete software solution for TCV. EnVision TCV includes Meridian CDC Verification for clock domain crossing (CDC) verification and PureTime™ for timing exception verification. The inspiration for EnVision TCV is the fact that while the use of static timing is key to the release of reliable high performance designs, there are still significant holes in typical verification and timing flows. These holes, such as untimed and unverified paths, allow designs with errors to slip through. By providing Proven Timing Closure, EnVision TCV complements existing flows, and avoids schedule delays or expensive chip respins.


Booth # 5260
Monday - Wednesday, June 4-6, 9:00AM to 6:00PM
Thursday, June 7, 9:00AM to 1:00PM
San Diego Convention Center, San Diego, CA

Information, Appointments and Registration Contacts:

For more information about Real Intent, please visit

To set an appointment with Real Intent, please contact:

For more information about DAC, please visit

About Real Intent's Verification Software

Real Intent's EnVision family includes: EnVision TCV, for Proven Timing Closure; Meridian CDC Verification for verifying the functionality of cross domain clocking schemes, with smallest amount of manual signoff required; PureTime, for detecting timing exception errors throughout the entire design flow, with RTL or design netlists; Conquest, for verifying electronic designs using Property Specification Language (PSL) assertions, SystemVerilog Assertions (SVA), or Open Verification Library (OVL) checkers, using static formal verification; Ascent for automatic checking of Register Transfer Level (RTL) designs to verify logic and find bugs even before simulation; and Ascent for automatic checking of Register Transfer Level (RTL) designs to verify logic and find bugs even before simulation.

About Real Intent

Real Intent extends breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent's products dramatically improve the functional verification efficiency of leading edge application-specific integrated circuit (ASIC), system-on-chip (SOC), and Field Programmable Gate Array (FPGA) devices. Over 40 major electronics design houses, including AMD, NVIDIA, Micronas, and NEC Electronics, use Real Intent software. For more information, visit or e-mail

EnVision, Envision TCV, Conquest, Ascent, PureTime, and Meridian CDC Verification are trademarks of Real Intent, Inc. All other trademarks or registered trademarks are property of their respective owners.

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