SOURCE: Sidense

January 17, 2008 11:00 ET

Sidense to Exhibit at Japan's EDS Fair January 24-25

Industry's Smallest Footprint, Lowest Power and Highest Performance OTP Memory IP Ideal for a Wide Range of Digital and Analog Applications

OTTAWA--(Marketwire - January 17, 2008) - Sidense, a leading developer of Logic Non-Volatile Memory (NVM) IP cores, will be exhibiting at the Electronic Design and Solution (EDS) Fair 2008 in Kanagawa, Japan January 24-25. The company will be showcasing the industry's smallest footprint and lowest power embedded non-volatile memory (NVM) for applications such as analog trimming, code storage, encryption keys, chip IDs, and configurable processors and logic circuits.

What:      Sidense will be showcasing their 1T-Fuse™-based dense, low
           power and highly secure one-time programmable (OTP) memory for
           standard-logic CMOS processes.

Where:     Booth #105
           Emerging Company Area
           EDS Fair
           Pacifico Yokohama
           Kanagawa, Japan

When:      January 24-25, 2008

Contact:   For additional information, contact Jim Lipman of
           Cain Communications at 925-606-1370, jlipman@caincom.com

About Sidense

Sidense provides secure, dense and reliable non-volatile one-time programmable (OTP) memory IP for use in standard-logic CMOS processes, with no additional masks or process steps required. Sidense's patented one-transistor 1T-Fuse™ architecture provides the industry's smallest footprint and lowest power Logic Non-Volatile Memory (NVM) solution.

Sidense OTP memory is available at 180nm, 130nm, 90nm and 65nm and scalable to 45nm and below. Ideal applications include analog trimming, code storage, encryption keys such as HDCP, RFID and Chip ID, medical, automotive, and configurable processors and logic. For more information, visit www.sidense.com.

Contact Information

  • Media Contact:
    Cain Communications for Sidense
    Jim Lipman
    Tel: 925-606-1370
    Email: Email Contact