SOURCE: CADENCE DESIGN SYSTEMS, INC.

January 22, 2008 08:00 ET

Toshiba Collaborates With Cadence to Improve Analog and Mixed-Signal Design Reliability at 65NM and Below

Toshiba Adopts Cadence Virtuoso UltraSim Full-Chip Simulator for Reliability Analysis Flow

SAN JOSE, CA--(Marketwire - January 22, 2008) - Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced today that Toshiba Corporation has deployed Cadence® Virtuoso® simulation technology to provide its analog and mixed-signal chip designers an easy-to-use and accurate reliability analysis flow. Toshiba chose the Virtuoso UltraSim Full-Chip Simulator for quantitative simulation methodology for reliability analysis at 65 nanometers and below to help ensure high performance and improve yield and quality of devices. Toshiba and Cadence worked together to implement Toshiba's advanced reliability models into Virtuoso UltraSim simulator using the UltraSim Reliability Interface and tested the results, resulting in the selection of the UltraSim simulator.

"With the Cadence Virtuoso UltraSim, Toshiba can provide highly reliable ICs for our customers, who provide consumer electronics applications, telecom-related products and peripheral devices," said Masazumi Shiochi, group manager of Mixed Signal CMOS Design Group, Toshiba's Semiconductor Company. "This reliability analysis flow enables us to meet our stringent reliability metrics, estimate the costs of test and debug, and meet our market window by providing high-quality devices to our end customers."

A part of Virtuoso Multi-Mode Simulation, the Virtuoso UltraSim Full-Chip Simulator is the Cadence FastSPICE circuit simulator that provides performance, capacity, and accuracy when verifying large custom, analog mixed-signal, RF, memory, and SoC designs. It uses true hierarchical simulation with patented isomorphic, adaptive partitioning algorithms and accurate RC reductions technology to provide the capacity, accuracy, and performance required for full-chip transistor level verification, regardless of design type or stage in the design cycle.

"We worked closely with Toshiba to ensure their engineers had the reliability analysis technology they need to provide visibility into the quality of their most complex designs," said Sandeep Mehndiratta, product marketing director at Cadence. "The UltraSim Reliability Interface allows customers to plug in their proprietary model while securing their IP. Toshiba was able to quickly implement the Virtuoso UltraSim reliability analysis in their flow, due to its ease of use and its ability to quantify the effect of performance and yield degradation for the lifecycle of their products."

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,300 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence and Virtuoso are registered trademarks, and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Contact Information

  • For more information, please contact:
    Dean Solov
    Cadence Design Systems, Inc.
    Direct: 408.944.7226
    dsolov@cadence.com