February 11, 2009 08:00 ET

Adaptive Chips Adopts Cadence Incisive Verification Solution With the Open Verification Methodology (OVM)

Flexible Multi-Language Environment Seamlessly Integrates and Leverages Verification IP Investments for New Designs

SAN JOSE, CA--(Marketwire - February 11, 2009) - Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that Adaptive Chips Inc. has adopted the Cadence® Incisive® functional verification solution with the Open Verification Methodology (OVM) to improve its verification process and seamlessly integrate verification IP (VIP) from multiple sources. After a thorough evaluation of several methodologies, Adaptive Chips determined that the OVM offered the broadest set of capabilities best suited to scale within a multi-language SystemVerilog and e verification environment.

By choosing the Cadence Incisive solution for the OVM, Adaptive Chips is now able to seamlessly integrate newly created OVM VIP with existing e-language verification components (eVCs) and Cadence VIP products to provide the differentiated solutions important to their customers. The Incisive solution has allowed the Adaptive Chips project teams to start the verification process much earlier and to better predict and achieve high-quality verification closure.

"It was essential that we had the ability to scale and leverage several forms of legacy VIP within our verification environments," said Amjad Qureshi, vice president of technology of Adaptive Chips. "The OVM's unique capabilities, robust methodology, openness, and maturity made it the obvious choice for our application. The rich debug capabilities and powerful multi-language verification engines in the Incisive technology also provided the solutions we needed to make the OVM the central part of our verification environment."

Co-created by Cadence, the OVM combines several advanced verification capabilities that the Adaptive Chips teams compared thoroughly to alternative verification methodologies. These capabilities include seamless VIP integration, significantly lowering the overall cost of development, and hierarchically scaling of the OVM environment to the system level, enabling SoC verification. The proven class-based verification capabilities within the OVM were also easy to access and use, allowing the team to get up and running much earlier in the development process.

"We're excited to see the OVM and the extended ecosystem take off so quickly," said Ziv Binyamini, Corporate Vice President of R&D at Cadence Design Systems, Inc. "There are many companies such as Adaptive Chips quickly discovering the flexibility of the OVM and the power Incisive technology adds to it for VIP integration, multi-language verification, and overall ease of use."

Open Verification Methodology

The Open Verification Methodology is the first open, language-interoperable, SystemVerilog verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. To download the OVM please go to

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence and Incisive are registered trademarks and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Contact Information

  • For more information, please contact:
    Dean Solov
    Cadence Design Systems, Inc.