SOURCE: Verific Design Automation

September 26, 2017 11:00 ET

Baum Licenses Verific's Parser Platforms

SystemVerilog, Verilog Parsers Function as PowerBaum Power Analysis' Front End

ALAMEDA, CA--(Marketwired - Sep 26, 2017) - Baum, a leader in power analysis solutions, today became the newest licensee of Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry.

Under terms of the agreement, Verific's SystemVerilog and Verilog parsers function as the front end to the recently launched PowerBaum from Baum. PowerBaum provides fast and accurate power models to enable system-level power analysis for an entire system-on-chip (SoC) design with realistic scenarios.

"We contacted Verific as soon as our product development got under way because they are the gold standard in parsers and customer support," claims Andy Ladd, Baum's chief executive officer. "Based on my prior experience at Carbon Design Systems, I knew Verific's front-end products were the best choice for Baum. In fact, Verific clearly qualifies for the Semiconductor Industry's Top Vendor for Support and Service award."

PowerBaum, a complete and accurate power analysis and modeling solution, is used early in the design cycle when there is more opportunity to optimize power and gain better energy efficiency. Engineering groups can use it for hardware/software co-design to optimize designs for low-power consumption, and power and thermal management. It supports dynamic and static power, taking in register transfer level (RTL) and netlist descriptions of the design.

"Baum identified an underdeveloped tool area for SoC design -- power modeling and analysis," says Rick Carlson, Verific's vice president of sales. "PowerBaum should be embraced by engineering groups who manage their performance goals through the design's energy efficiency."

Verific's SystemVerilog, VHDL and UPF parsers are in production and development flows throughout semiconductor companies worldwide, from emerging companies to established Fortune 500 vendors. Applications include analysis, simulation, formal verification, synthesis, emulation and virtual prototyping, in-circuit debug and design for test. Verific distributes its Parser Platforms as C++ source code and compile on all 32 and 64 bit Unix, Linux, Mac and Windows operating systems.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effectively. Since 1999, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: info@verific.com

About Baum

Baum provides electronic design automation (EDA) software and solutions that enable engineering groups in the automotive, internet of things (IoT), mobile, networking and server markets to fully optimize the energy efficiency of their semiconductor designs. Founded in 2016 by seasoned semiconductor professionals with technical, R&D and business development expertise, Baum is privately held and funded. Email: contacts@baum-ds.com Website: www.baum-ds.com 

Engage with Verific at:
Website: www.verific.com
LinkedIn: https://www.linkedin.com/company/810695/
Facebook: https://www.facebook.com/Verific-Design-Automation-100448363329771/ 

Verific Design Automation and Baum acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

Contact Information

  • For more information, contact:
    Nanette Collins
    Public Relations for Verific
    (617) 437-1822
    Email Contact