June 09, 2008 08:00 ET

Cadence Delivers OVM-Compliant Verification IP

Cadence Verification IP Enables Open Verification Methodology (OVM) Users to Automate Protocol Verification and Compliance to Meet Schedule Demands

SAN JOSE, CA--(Marketwire - June 9, 2008) - Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced the availability of the first two advanced testbench verification IP (VIP) products that are compliant with the Open Verification Methodology (OVM). These enhancements enable the rapidly growing community of OVM users to easily access Cadence® metric-driven verification solutions and to predictably achieve high-quality verification closure. The AMBA® 3 AXI™ and AMBA AHB™ VIP, having been proven on hundreds of designs, are now available as multi-language Universal Verification Components (UVC) and are the first to provide OVM support within the Cadence VIP portfolio. OVM support will be added to the remaining protocols in the VIP portfolio in the second half of 2008.

Cadence VIP simplifies the overall verification development and integration process for design and verification teams that are developing OVM-based testbenches using an automated metric-driven approach. Included with the VIP is the unique compliance management system (CMS), which automates compliance verification -- one of the key benefits of the metric-driven approach. CMS delivers high functional coverage with push-button ease, allowing users to avoid the most difficult aspects of protocol compliance verification. The compliance management capability within the Cadence OVM verification IP reduces the necessary resources and expertise required to reach verification closure. For example, the CMS aids in generating complex corner-case scenarios, leading to the elimination of most manual test writing. This allows users to avoid the time-consuming and unpredictable aspects of using alternative VIP, thus improving quality, increasing productivity, and delivering much higher levels of predictability.

"The Cadence metric-driven verification IP took only a few days to get up and running in our SystemVerilog testbench," said Suhas Belgal, verification manager of Magnum Semiconductor. "The VIP significantly enhanced Magnum's ability to fully verify our designs that include both AHB Master and Slave ports."

Unlike most alternative offerings, the Cadence VIP provides much more than a simple bus functional model, or BFM. Cadence VIP includes the CMS, constrained-random stimuli generation, complete protocol checking, scoreboarding hooks, and a full functional coverage solution. Cadence VIP now addresses an even broader community of users with multi-language testbench support for both SystemVerilog and e.

"High-quality verification IP has become mission critical for verification engineers who must keep pace with their increasingly complex verification challenges and shrinking schedules," said Dave Tokic, director of product marketing at Cadence. "Extending our industry-leading VIP with OVM support provides unique multi-language capabilities our customers require to meet their verification closure and reuse needs."

Cadence provides a broad portfolio of advanced testbench, assertion-based, transaction-based acceleration, and emulation Speedbridge VIP for verification of complex protocols such as AMBA, PCI Express, PCI, USB, Ethernet, SATA and OCP, with additional protocol support planned. In addition, over 30 other protocols are available through the Cadence Verification Alliance Program. With hundreds of person-years invested in its development and more than 2,000 designs verified, Cadence verification IP provides industry-leading maturity and production-proven success.

Open Verification Methodology

The Open Verification Methodology, based on IEEE Std. 1800™-2005 SystemVerilog, is the first open, language-interoperable, SystemVerilog verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. To download the OVM please go to

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence® software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence is a registered trademark, and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Contact Information

  • For more information, please contact:
    Dean Solov
    Cadence Design Systems, Inc.