April 23, 2007 08:00 ET

Cadence Encounter Platform Delivers Leading Low-Power and DFM Features for 65-NM Design

Updated Digital IC Design Platform Improves Performance for Advanced IC Design

SAN JOSE, CA -- (MARKET WIRE) -- April 23, 2007 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today unveiled its latest software version of Cadence Encounter® digital IC design platform with industry-leading features including chip optimization, mixed-signal design support for very large 65nm-and-below designs, diagonal routing using the Encounter X Interconnect Option, and previously announced support for Si2's Common Power Format (CPF) 1.0-enabled low-power design. Available in L, XL and GXL offerings, the new platform provides greater ease of use, shorter design time and improved performance for advanced semiconductor design.

"The latest release of Encounter platform represents an important development to the members of STARC, because it addresses, in a comprehensive fashion, the challenges inherent in designing for low power and manufacturing, with high productivity," said Nubuyuki Nishiguchi, vice president and general manager of STARC. "This integrated, front-to-back approach creates significant value to leading-edge designers."

A key feature of the latest Encounter platform release is support of the Cadence Low-Power Solution, based on Si2's CPF 1.0 standard. The Cadence Low-Power Solution offers a complete flow across logic design, verification, and implementation. CPF is an industry standard format for specifying power-saving techniques throughout the design process -- enabling teams to share and reuse low-power intelligence.

In addition, the new release of the Encounter platform provides unparalleled design for manufacturing (DFM) support, yield optimization, lithography-aware routing, mixed-signal design using new bus routing capabilities, and critical path simulation using the Virtuoso® UltraSim Full-chip Simulator. The platform also features new power-aware automatic macro placement capability and support for simultaneous multi-mode and multi-corner timing analysis and optimization. The Encounter X Interconnect Option delivers higher quality of silicon (area, power, performance requirements) and cost-savings.

"We continue to make significant improvements in the Encounter platform to lead the industry in advanced low power and 45/65nm designs. The latest developments allow direct benefits to most advanced IC designs," said Dr. Chi-Ping Hsu, corporate vice president, IC Digital and Power Forward at Cadence. "This release packs many major breakthroughs -- holistic advanced low power, DFM, Encounter X Interconnect Option and mixed-signal design -- into a single highly integrated design environment."

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence, Encounter and Virtuoso are registered trademarks, and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Contact Information

  • For more information, please contact:
    Dan Holden
    Cadence Design Systems, Inc.