March 07, 2007 08:00 ET

Cadence Partner Faraday Uses Encounter Conformal Technology for Constraint Signoff of ASIC Designs

Cadence Encounter Conformal Constraint Designer Enables Logic Designer's Early Detection of Constraint Issues for Signoff

SAN JOSE, CA -- (MARKET WIRE) -- March 7, 2007 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today said Faraday Technology Corporation (TAIEX: 3035) has adopted the Cadence® Encounter® Conformal® Constraint Designer technology for fast, highly reliable signoff of leading-edge designs. Faraday uses the Encounter Conformal Constraint Designer technology to validate customers' design constraints, ensuring the quality of the design before implementation. This reduces design iteration and accelerates timing closure.

"Faraday is committed to providing customers with the design expertise and services necessary to bring leading ASIC designs to market," said Kun-Cheng Wu, director of the Design Development Division at Faraday. "The Cadence Encounter Conformal Constraint Designer allows us to quickly and easily ensure that our customers' designs are ready for production."

By using the Encounter Conformal Constraint Designer technology as a constraint signoff tool, Faraday is able to detect issues in their customers' design constraints, provide reports on these issues, and allow their customers to correct the constraints early in the design phase. This signoff procedure improves the quality of Faraday's implementation service while saving both valuable time and resources of its IC design and ASIC customers.

"One of the most important capabilities that we can provide to the design industry is the ability to ensure that design constraints are appropriate and accurate," said Michael Chang, vice president of R&D for Cadence. "The Encounter Conformal Constraint Designer technology provides confidence in the integrity of the design, and that's a valuable asset for a design house such as Faraday."

Encounter Conformal Constraint Designer is a key technology in the Cadence Encounter digital IC design platform and a component of the Cadence Logic Design Team Solution. It enables early logic-design signoff and automates the generation, validation, and refinement of constraints to ensure that timing constraints are valid throughout the entire design process, helping designers achieve rapid timing closure. Encounter Conformal Constraint Designer is available in L and XL offerings.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence, Encounter and Conformal are registered trademarks, and the Cadence logo is a trademark of Cadence Design Systems in the United States and other countries. All other trademarks are the property of their respective owners.

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