SOURCE: ChipPath Design Systems

ChipPath Design Systems

May 27, 2014 10:00 ET

Chip Path Design Systems Announces Free Access to Its Multi-Vendor Architectural FPGA and FPASSP Mapping Tools

Vendor-Neutral Portal and IP Directory Provides Immediate Access to Design, Compare and Buy Thousands of 20nm to 350nm FPGA Parts

CUPERTINO CA--(Marketwired - May 27, 2014) - (at the Design Automation Conference) - Chip Path™ Design Systems, a chip architecture and assembly company, announces the industry's first device-mapping tools and IP directory for FPGA front-end design with free and pay by credit card use models. Using only a web browser with no software installation required, the Chip Path portal and IP directory are freely accessible from anywhere in the world. For the first time, designers can design, research, compare and plug-and-play hundreds of IP blocks onto FPGA devices across multiple vendors.

Chip Path has aggregated 6,000 intellectual property (IP) cores from over 400 vendors for use in FPGA mapping and estimation. The result is the ability to significantly reduce design costs and speed design time by providing technical and business information in one graphical and easy-to-use system. The portal features devices from Altera Corp., Lattice Semiconductor Corp., Microsemi Corp. (Actel), Xilinx Inc. and Achronix. Over 29 FPGA families are supported, representing 430 bases with over 2,000 package combinations and over 11,000 part numbers and speed grades. Real-time inventory and part number purchasing can be done directly from the website, linking distributors such as Arrow, Avnet, Digi-Key, Mouser and others.

FPGA and FPASSP: Fast track from chip architecture to implementation

Chip Path has created a new paradigm in FPGA device mapping technology serving both FPGA and ASSP. To improve FPGA efficiency, the trend has been to hard diffuse large SoC-style blocks alongside the more expensive FPGA fabric. The FPASSP (Field Programmable ASSP) represents a hybrid of the flexibility of an FPGA with embedded ASSP hard-diffused partitions. Using Chip Path's unique system, architects can design chips using semantic or placeholder IP, directly using vendor IP or their own internal IP to create, assemble and test economic viability of their designs, reducing risk, cost and time to market. Chip Path can map pure FPGA devices as well as those with complex SoC style partitions. Now entire systems can be efficiently mapped onto one die. Chip Path's FPASSP portal supports SmartFusion™, SmartFusion 2™, Zynq®-7000, Arria® V SE/SX and Arria® 10 SE/SX.

"For the first time customers will have access to vendor-neutral tools that provide impartial FPGA mapping from the four major vendors and Achronix," said J. George Janac, CEO of Chip Path Design Systems. "As FPGAs have embraced the latest 28nm nodes much faster than ASICs or ASSPs, they have increasingly become a competitive solution for box, board, and systems designers."

The Chip Path Portal provides the industry's first worldwide subscription-based usage system using both free and advanced pay features with secure credit card processing. The self-service portal allows users to aggregate data on all available IP and FPGAs from vendors, removing problems associated with limited data access. Users are assured to receive the most accurate and competitive information available.

FPGA and FPASSP: Architectural creation by catalog models

Design entry is simple and flexible. FPGA Search can be run from a single form with as little as six resource numbers. Chip Path search tools also offer the option to import vendor synthesis and mapping results allowing development board-based RTL designs to be mapped onto much cheaper devices for production.

Chip Path's ChipArchitect tool uses built-in semantic models and can generate over 1.8M end-to-end I/O channel and core models with either a hard embedded IP or FPGA fabric implementation. Additional tools provide the added flexibility of adding blocks either directly from an external vendor IP catalog or from an internal IP catalog. Pre-RTL blocks can be defined using LUT, BRAM, DSP and other resources. ChipArchitect provides a complete array of input options and outputs the best choices of devices across the industry for its customers.

Pricing

The Chip Path FPGA portal has a free use starter model. The FPGA search tool and IP directory can be used free of charge without a login, allowing mapping of devices and IP directory search. Free use of the FPGA ChipArchitect tool is also provided, but login is required.

A $79/year membership provides added device access to 28nm FPGA devices as well as new 40nm/65nm devices from Lattice Semiconductor and Microsemi. Full FPGA package selection, SERDES mapping, speed grade analysis, real-time inventory and distributor ordering start at $199/week. A similar package that adds FPASSP devices is $299/week. In addition, 20nm/22nm pre-production device models are directly available from Chip Path for a monthly subscription fee.

Availability

The Chip Path Portal is now available at www.ChipPath.com. The worldwide design community is invited to visit the portal, view our technical video demonstration and explore the free resources and available services.

Chip Path at 2014 DAC

Chip Path will be displaying its web planning portal, FPGA mapping tools and IP directory at the 2014 Design Automation Conference (DAC) from June 2-4 in San Francisco, CA in booth #206C.

About Chip Path

Chip Path Design Systems is a privately funded chip architecture and assembly company that merges web technology with semiconductor design and intellectual property reuse to dramatically simplify IC design. Targeting the front-end process from specification through IP assembly to physical planning, and device selection, the Chip Path platform significantly lowers risk and cost of complex SoC and FPGA design while improving quality, power and performance.

The company is headquartered in Cupertino, Calif. 95014. Telephone: 408-257-3643. Email: info@ChipPath.com. Website: www.ChipPath.com.

ChipPath, ChipSearch, ChipArchitect, ChipAssembler, ChipPlanner, IPDirectory SemantIC I/O Semantic IP, Semantic CN, and SemantIC Design are trademarks of Chip Path Design Systems.

Contact Information

  • For more information, please contact:
    Laurie Isaacson
    Director Public Relations for Chip Path
    +1 408 257 3643
    Email Contact