SOURCE: Sidense

November 27, 2007 11:00 ET

Embedded OTP Memory Provider to Participate in an IP 07 Panel on Implementing Security of On-Chip Resources

Thursday, December 6, 9:45AM - 10:45AM, Grenoble, France

OTTAWA, ON--(Marketwire - November 27, 2007) -

Sidense, a leading developer of Logic Non-Volatile Memory (NVM) IP cores,
has organized and will be participating on a panel about "Implementing
Security of On-Chip Resources" as part of the IP-based SoC Design
Conference and Exhibition (IP 07) in Grenoble, France. During the panel,
Sidense will discuss the role of OTP (one-time programmable) memory in
securing chip hardware and software.

Panel: Implementing Security of On-Chip Resources

Moderator: Jim Tully, VP Distinguished Analyst, Gartner

- Gagan Gupta, Senior Director of Product Marketing, ARC International
- Steven H. Cliadakis, VP of Sales and Marketing, Sidense
- Mike Bursell, European Technical Manager, Certicom

Thursday, December 6, 9:45AM to 10:45AM


World Trade Center
5 place Robert Schuman
38 000 Grenoble

IP 07 Program Information and Registration



About Sidense

Sidense provides secure, dense and reliable non-volatile one-time programmable (OTP) memory IP for use in standard-logic CMOS processes, with no additional masks or process steps required. Sidense's patented one-transistor 1T-Fuse™ architecture provides the industry's smallest footprint and lowest power Logic Non-Volatile Memory (NVM) solution. Sidense OTP memory is available at 180nm, 130nm, 90nm and 65nm and scalable to 45nm and below. The IP is available at UMC, TSMC, SMIC, Tower and Chartered. Ideal applications include analog trimming, code storage, encryption keys such as HDCP, RFID and Chip ID, medical, automotive, and configurable processors and logic. For more information, visit

Contact Information

  • For more information or to schedule a meeting with Sidense, please
    contact :

    Jim Lipman
    Cain Communications
    Email Contact