SOURCE: Silistix

May 14, 2007 14:49 ET

Free Seminar to Learn Solutions to SoC Design Problems

SAN JOSE, CA -- (MARKET WIRE) -- May 14, 2007 --Silistix and CoWare are sponsoring a free seminar to learn solutions to some of the most challenging problems facing SoC design teams today.

Seminar Topic: Scaling the SoC Design Wall
Date:          May 22, 2007
Location:      Network Meeting Center
               5201 Great America Parkway
               Santa Clara, CA 95054

Jim Turley -- "The SoC Wall"

Acknowledged authority on microprocessor chips, embedded systems, semiconductors, and intellectual property licensing and current publisher of Silicon Insider.

Professor Takashi Nanya -- "Challenges and Perspective in Network on Chip Technologies"

Professor at the Research Center for Advanced Science and Technology (RCAST), University of Tokyo, and a Senior Fellow of the Japan Science and Technology Agency.

Steve Furber -- "System-Level Design & Timing Encapsulation"

ICL Professor of Computer Engineering in the School of Computer Science at the University of Manchester and a principal designer of the BBC Microcomputer and the ARM 32-bit RISC microprocessor.

Grant Martin -- "A Marriage Made in Heaven? ESL, IP and Interconnect"

Chief Scientist at Tensilica, Grant has previously worked at Cadence, Nortel/BNR and Burroughs. He is also the author of several books on SoC design and SystemC.


The rapid increase in design complexity has become a limiting factor in system-on-a-chip (SoC) designs. This sharp increase is driven by several factors, a major one being the exponential rise in the number of IP blocks integrated in a single SoC and the difficulty in connecting those IP blocks. Other limiting factors include controlling chip power consumption, the routing of global clocks across large silicon areas, and the inability to fully validate your SoC specification early in the design cycle. Recent research from both academia and industry has introduced new methodologies and tools you can use to significantly reduce your design iterations and thus reduce your time to market.


To register for the free Scaling the SoC Wall seminar, go to Breakfast and lunch will be provided.

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