May 29, 2007 08:00 ET

Fujitsu Kyushu Network Technologies Selects Cadence SystemVerilog to Ease Designer Adoption

Incisive Plan-to-Closure Methodology Delivers Advanced SystemVerilog Verification Capabilities to Design Teams, Including Test Generation, Checking, and Coverage

SAN JOSE, CA--(Marketwire - May 29, 2007) - Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced that Fujitsu Kyushu Network Technologies Limited has adopted the Cadence® Incisive® Plan-to-Closure Methodology for SystemVerilog verification in RTL logic design teams. The Cadence methodology was used to verify Fujitsu's latest set of MPEG decoder modules delivering motion block decoding capabilities. It includes a proven multi-language approach to verification reuse and specifically targets logic designers who need "design with verification" capabilities that ease SystemVerilog adoption.

Based on feedback from recent projects, Fujitsu found that adoption of the Plan-to-Closure Methodology was very practical for designers needing advanced verification capabilities and also demonstrated the scalability needed to leverage SystemVerilog-based environments from individual modules to full systems. The ability to perform automated functional coverage analysis and checking speed the verification process and cut the overall verification time by nearly half. The methodology also ensured that the design was of the highest quality before taping out.

"Our logic designers found bugs much earlier with the Cadence SystemVerilog-based methodology," said Takahiro Kobayakawa, senior engineer at Fujitsu Kyushu Network Technologies Limited. "It has offered our designers an easy-to-adopt automation layer that allows much more control and insight into the verification process."

The team also realized other benefits, including easy integration of existing C-based Verilog functions into the SystemVerilog test environment, which allowed efficient reuse of proven verification code. This also saved the team a compile step further compressing the verification cycle.

"We're delighted that our solutions have lowered the adoption bar for designers who need SystemVerilog-based solutions," said Steve Glaser, corporate vice president, marketing, Verification Division at Cadence. "We'll continue to carve out a practical path for logic design teams to implement 'design with verification' approaches to ensure high quality throughout the design process, from module to full system-level."

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

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Contact Information

  • For more information, please contact:
    Doron Aronson
    Cadence Design Systems