SOURCE: GateRocket


January 18, 2011 07:30 ET

GateRocket at DesignCon -- FPGA Design So Easy a Caveman Can Do It

Advanced FPGA Design Solutions Highlighted in Booth #830; CEO Dave Orecchio Featured Panelist on Tools Discussion

BEDFORD, MA--(Marketwire - January 18, 2011) - GateRocket® Inc. will showcase its industry-leading solutions for reducing FPGA verification and debug times at this month's DesignCon, and GateRocket President and CEO Dave Orecchio joins a high-powered panel exploring how design tools will keep pace with advances in FPGA complexity. 

WHO: GateRocket, supplier of advanced FPGA design and debug solutions for Xilinx and Altera programmable devices.

WHAT: GateRocket brings its Device Native® verification approach to DesignCon which extends the existing simulation environment in a way that enables engineers to detect bugs up-front in the design process that would otherwise slip through to system integration. The company's RocketDrive® is a hardware-based solution that significantly accelerates simulation and debug of large FPGAs; it bridges the gap between the RTL and the FPGA, enabling silicon-accurate simulation because it integrates the target FPGA device into the simulator. 

GateRocket will demonstrate a communications design that uses a XAUI core and SERDES elements, and show how to debug the design and the acceleration benefits of hardware-based verification methodologies.

If you are not attending the show and are doing DSP-based design with The MathWorks products, you can watch GateRocket's on-line demonstration on their web site that shows the benefits of acceleration and debugging for DSP-based FPGA designs. 

GateRocket Booth #830, DesignCon, Jan. 31 - Feb. 3, Santa Clara Convention Center. 

DesignCon Technical Panel: "FPGA Caveman Meets FPGA Chiphead, FPGA Design Tools And Methodologies: Can They Keep Pace?" Tuesday, Feb. 1, 3:45pm - 5:00pm, Ballroom F. Panelists: Jim Hogan, Moderator; Dave Orecchio, President and CEO, GateRocket; Botao Lee, Senior Staff Engineer, Manager, Qualcomm; Nagesh Gupta Engineering Group Director, Cadence; Vin Ratford, Senior Vice President, Worldwide Marketing, Xilinx; Jay Schleicher, Director Software Engineering Group, Altera.


WHY: A recent FPGA Journal survey indicated that the process for identifying and fixing FPGAs by looping from the lab, where a bug is identified, back through simulation, synthesis, and place and route adds between 92 and 148 days to the FPGA design process. GateRocket has shown that its solutions can reduce this process by 55% or more by allowing the same bugs to be found and fixed during the simulation phase. According to FPGA Journal editor Kevin Morris: "By allowing the simulator to perform like the development board, many of us would be inclined to do more of our debug there, saving us some big time in the lab later on."

About GateRocket:  GateRocket, Inc., located in Bedford, Mass., offers electronic engineers the first Device Native® verification and debug solution for advanced FPGA semiconductor devices. The company's RocketVision software debug tool and its RocketDrive hardware verification system enables users to verify and debug advanced FPGA designs faster and with higher quality for greatly improved time-to-market, and realize more reliable and predictable results. Learn more about GateRocket online at and sign up for a free webinar.

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