SOURCE: GateRocket

GateRocket

September 07, 2010 08:30 ET

GateRocket CEO Details Best Tools for FPGA Design at ESC Boston Wednesday, September 22

BEDFORD, MA--(Marketwire - September 7, 2010) -  GateRocket® Inc. President and CEO Dave Orecchio will conduct a class, "Best Tools for Verification and Debug of FPGAs" at this month's ESC Boston.

WHO: GateRocket®, supplier of advanced FPGA design and debug solutions for Xilinx and Altera programmable devices.

WHAT: With improvements to the FPGA design flow, such as those that device native methodologies deliver, FPGAs will continue to grow as an important design consideration in production systems, even as platforms for complex embedded systems that contain multiple functional blocks and subsystems.

WHEN: 3:15pm, Wednesday, Sept. 22, ESC Boston

WHERE: Room 103, Hynes Convention Center, Boston

WHY: A recent FPGA Journal survey indicated that the process for identifying and fixing FPGAs by looping from the lab, where a bug is identified, back through simulation, synthesis, and place and route adds between 92 and 148 days to the FPGA design process. GateRocket has shown that its solutions can reduce this process by 55% or more by allowing the same bugs to be found and fixed during the simulation phase. According to FPGA Journal editor Kevin Morris: "By allowing the simulator to perform like the development board, many of us would be inclined to do more of our debug there, saving us some big time in the lab later on."

About GateRocket:  GateRocket, Inc., located in Bedford, Mass., offers electronic engineers the first Device Native® verification and debug solution for advanced FPGA semiconductor devices. The company's RocketVision software debug tool and its RocketDrive hardware verification system enables users to verify and debug advanced FPGA designs faster and with higher quality for greatly improved time-to-market, and realize more reliable and predictable results. Learn more about GateRocket online at www.gaterocket.com and sign up for a free webinar.

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