SOURCE: GateRocket


January 31, 2011 08:30 ET

GateRocket SoftPatch for FPGA Debug and Verification Wins 2011 DesignVision Award for Best IC Design Tool

BEDFORD, MA--(Marketwire - January 31, 2011) - GateRocket, Inc., the leading supplier of verification and debug tools for advanced FPGAs, announced today its SoftPatch enhancement to its Device Native FPGA verification solution has won the 2011 UBM Electronics DesignVision Award for Best IC Design Tool. The award will be presented at DesignCon on Tuesday, Feb. 1 in Santa Clara, Calif.

SoftPatch is a new feature for GateRocket's RocketVision® FPGA debug platform. It enables designers to patch their FPGA hardware with an edited RTL software block and see the effect on the chip's operation without re-building the FPGA. The capability allows the user to select any number of individual design blocks to have the flexibility to run in their simulator or execute in the FPGA that is inside GateRocket's RocketDrive® hardware verification system. The user can then decide at simulation time which blocks execute inside the FPGA or in the simulator. This powerful capability enables them to select a block, instruct it to run in the simulator and then make changes to the RTL of that block and simulate it in software while the rest of the design executes in the native FPGA hardware in the RocketDrive. The user can repeat that sequence for as many blocks as they choose, again at runtime without rebuilding the FPGA device.

The benefit is straightforward: finding and fixing bugs faster, and avoiding unnecessary re-runs of time-consuming synthesis-to-place-and-route iterations. In customer engagements, it has proven to reduce overall design bring-up time by up to 50% or more compared to traditional approaches. It's not uncommon for large FPGAs design projects to have 18 hour synthesis-place-route times and anywhere between 100 to 200 iterations for a given project. Taking the average number of iterations, this means design teams are spending 2,700 hours building the FPGA, or 112, 24 hour days or 22.5 weeks. By cutting this time in half they could save 11.25 weeks or more of project time.

The Design Vision Awards are sponsored by The EE Times Group, a division of United Business Media (UBM). UBM editors judge entrants based on three criteria:
1. Market Vision: unique insight into customer needs, as opposed to me-too product definition
2. Originality of a Solution: new approach to meeting the market needs, as opposed to an
evolutionary product
3. Quality of Implementation: how well does the product fit the market requirements

"GateRocket has distinguished itself by coming up with an entirely new way of tackling the FPGA debug and verification challenge," said Brian Fuller, EE Times Product Strategist. "SoftPatch exemplifies their innovative approach to creating methodologies that both improve design quality and time to market and is richly deserving of this award."

About GateRocket

GateRocket, Inc., located in Bedford, Mass., offers electronic engineers the first Device Native® verification and debug solution for advanced FPGA semiconductor devices. The company's RocketVision® software debug tool and its RocketDrive hardware verification system enables users to verify and debug advanced FPGA designs faster and with higher quality for greatly improved time-to-market, and realize more reliable and predictable results. Learn more about GateRocket online at and sign up for a free webinar.

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