Cadence Design Systems, Inc.

September 13, 2010 08:00 ET

Global Unichip Boosts Design Productivity With Cadence Encounter Timing System

Integrated Signoff Analysis Helps GUC Reduce Time to Final Design Closure for Faster Silicon Realization

SAN JOSE, CA--(Marketwire - September 13, 2010) -  Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global design innovation, today announced that Global Unichip Corporation (GUC) has adopted the Cadence® Encounter® Timing System to reduce time to final design closure efficiently in its Encounter Digital Implementation (EDI) System-based design flows. By adopting the integrated signoff solution, GUC is able to shorten lead time and reduce tapeout schedule risk for Silicon Realization.

By integrating Encounter Timing System into its traditional timing and noise signoff solution, GUC has established a robust environment for timing optimization during the placement and routing stage and final signoff verification. The analysis capabilities of the Encounter Timing System are integrated into the EDI System, giving GUC a single, consistent analysis view. This view enables signoff to drive implementation, which improves consistency and accelerates design closure through final timing signoff.

"Time to production is the key to the success of our company; most importantly, to the success of our customers," said Chi-Chiang Hsieh, vice president of Global Unichip. "So, we are glad to see the turnaround time reduction in signoff iterations that Encounter Timing System brings to our Silicon Realization flow." 

EDI System delivers a comprehensive solution for advanced design closure. Sharing a common infrastructure with EDI System, Encounter Timing System enables faster engineering change orders (ECOs) between the implementation and signoff environments, resulting in better signoff verification and a dramatic reduction in late-stage design iterations. In addition, the intuitive graphical debug capabilities of Encounter Timing System help designers to accelerate root-cause and bottleneck analysis, potentially shaving weeks off tapeout schedules.

"We are delighted that GUC has achieved this important productivity enhancement with the Cadence Encounter Timing System," said David Desharnais, product management group director at Cadence. "Addressing the productivity gap for customers is a key element of our EDA360 strategy. GUC's continued adoption of Cadence solutions to improve design cycle efficiency is another example of our commitment to provide our customers with a Silicon Realization environment that addresses today's most complex design challenges and improves their competitive edge in the market."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

About GUC

Global Unichip Corp. (GUC), a dedicated full-service Fabless ASIC provider based in Taiwan, was founded in 1998. GUC is now publicly traded on the Taiwan Stock Exchange under the symbol 3443 with annual sales close to US$ 300M in 2009. GUC provides total solutions from silicon-proven IPs to complex time-to-market SoC turnkey services. GUC is committed to providing the most advanced and the best price-performance silicon solutions through close partnership with TSMC, GUC's major shareholder, and other key packaging and testing power houses. With state of the art EDA tools, advanced methodologies, and experienced technical team, GUC ensures the highest quality and lowest risks to achieve first silicon success. GUC has established a global customer base throughout Greater China, Japan, Korea, North America, and Europe. Its track-record in complex SoC designs has brought benefits to customers in time to revenue at the lowest risk. 

Cadence and Encounter are registered trademarks of Cadence Design Systems, Inc., in the USA and other countries. All other marks and names are the property of their respective owners.

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