SOURCE: Verific Design Automation
VANCOUVER, BC--(Marketwired - May 15, 2014) - Invionics, a company providing software to accelerate integrated circuit (IC) development and design automation, today took the wraps off the VRDM Development Platform that layers a rapid development interface on top of Verific's industry-standard, IEEE-compliant SystemVerilog and VHDL parsers.
"VRDM lets designers use the features they expect and languages they know to accelerate their next EDA product or custom tool development," remarks Michiel Ligthart, Verific's president and chief operating officer.
To gain advantage in highly competitive markets, semiconductor and system design companies increasingly are building their own in-house design tools and flows. The VRDM Development Platform reduces costs and accelerates development of these tools and flows by providing a high-level, easy-to-use, scriptable interface to Verific's market-leading parsers.
"We set out to accelerate design tool and flow developments that require Verific's SystemVerilog and VHDL parsers, a market we knew could really benefit from automation," says Dr. Brad Quinton, Invionics' chief executive officer. "Our engineering team has extensive real-world IC design experience coupled with a deep understanding of EDA software development and Verific's parsers, an impeccable background to design the VRDM Development Platform."
VRDM is designed to be intuitive and efficient to designers and computer aided design (CAD) engineers. It can be used to build a variety of design tools and flows, such as static verification, linting, design for test (DFT) insertion, field programmable gate array (FPGA) prototyping pre-processing, power management insertion and more. With an intuitive Python or Tcl application programming interface (API), VRDM enables quick development of high value-add internal tools and utilities. With VRDM knowledge of C++ is not a requirement.
Additional key functionality includes advanced regular expression-based design search, detailed interactive design reporting, an XML export capability and support for the Synopsys Design Constraint (SDC) format.
Verific's software is the front end to electronic design automation (EDA) and FPGA tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Its Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl APIs. Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.
Availability and Pricing
The VRDM Development Platform is available now from Invionics. Pricing is available upon request.
For more information, visit the Invionics website located at: www.invionics.com.
Invionics and Verific at DAC
Invionics will exhibit the VRDM Development Platform in the Verific booth (#1909) during the 51st Design Automation Conference (DAC) Monday, June 2, through Wednesday, June 4, from 9 a.m. until 6 p.m. at the Moscone Center in San Francisco.
The DAC website is found at: www.dac.com.
Invionics accelerates IC development and design automation. Leveraging hands-on hardware design experience and proven EDA tool development success, its products include IC design tools, hardware IP and EDA development platforms that provide immediate value to semiconductor, system and EDA companies. Invionics also provides experienced custom R&D to extend its products and IP, enabling design teams to quickly implement key functionality and gain competitive advantage for their products. Corporate headquarters is located in Vancouver, British Columbia, Canada. Telephone: (604) 336-3325. Email: email@example.com. Website: www.invionics.com.
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: firstname.lastname@example.org. Website: www.verific.com.
Invionics and Verific Design Automation acknowledge trademarks or registered trademarks of other organizations for their respective products and services.