SOURCE: Lattice Semiconductor Corporation

April 24, 2006 08:00 ET

Lattice Adds Programmable Power Supply Trimming IC to Power Manager II Product Family

Low Cost Device Controls Output Voltage Accuracy of Discrete DC-DC Converters

HILLSBORO, OR -- (MARKET WIRE) -- April 24, 2006 -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the ispPAC®-POWR6AT6 device, the latest addition to its Power Manager II product family. The ispPAC-POWR6AT6 device provides margining, selectable output levels and voltage monitoring support for low cost embedded or discrete IC-based power supply designs. Providing control for up to six separate power supplies at once, the ispPAC-POWR6AT6 device has six power supply TrimCell control pins, six differential monitoring inputs, a precision 10-bit ADC for voltage measurement, and an I2C/SMBus compatible serial interface to control device features and communicate power supply levels.

"Tighter control of DC-DC converter output voltages increases a circuit board's operational reliability," said Stan Kopec, corporate vice president of marketing. "The POWR6AT6 device provides a programmable, integrated solution with unprecedented flexibility and cost-effectiveness, packaged into a small 5mm x 5mm PCB footprint."

Digital Feedback Controls DC-DC Output Voltage Variation to < 0.5%

The ispPAC-POWR6AT6 device integrates a unique Margin and Trim Block (MTB) that provides a flexible mechanism for both setting and maintaining the output voltage of a power supply to within 1% of its set value ("trimming"), as well as the ability to vary a power supply voltage to +/- 0.5% of its target value for quality control purposes ("margining"). The MTB consists of six TrimCells that simultaneously control the power supply voltages of up to six power supplies. Each TrimCell has an 8-bit DAC and six DAC registers for margining and trimming flexibility. Accuracy of the trimmed voltage across operating temperature, load and age of the power supply is achieved through a Digital Closed Loop Trim control circuit.

The Digital Closed Loop Trim control circuit continuously compares the voltage set point of a given power supply with the output of the on-chip ADC that is monitoring that power supply voltage. The error signal that results automatically increases or decreases the DAC voltage, maintaining the power supply voltage at a constant value. Further, an external microcontroller can monitor the power supply voltage through the on-chip ADC and directly control the corresponding DAC through the I2C interface. The TrimCell also can store four different DAC code settings or configurations that can easily be selected using hardware pins dedicated to voltage profile selection.

POWR6AT6 Device Enables Digitally Controlled Power Supply Margining

It has become commonplace to test electronic assemblies in manufacturing over varying supply voltages to ensure functionality over operational extremes. Once considered a characterization activity and performed by making manual adjustments, it is now more common to automatically test every system in this manner before shipment. The ispPAC-POWR6AT6 device is ideally suited to implement this type of automated margining control cost-effectively. The ispPAC-POWR6AT6 device can be configured to adjust up to six supplies with up to four pre-configured output voltages that match the operating requirements of the application.

About the Power Manager II Device Family

The Lattice ispPAC Power Manager II family integrates intelligent power sequencing and precision fault monitoring technology together with power supply voltage margining and trimming using digital closed loop technology -- all in a single low-cost chip. The Power Manager II devices contain precision threshold comparators for monitoring power supplies for faults, a10-bit Analog-to-Digital (ADC) converter for measuring power supply voltages, Digital-to-Analog Converters (DAC) to control power supply output voltages, a CPLD to intelligently control power supply sequencing and generation of supervisory signals, programmable timers for controlling the speed of the power supply turn on/off process, charge pumped drivers for driving n-Channel MOSFETs, digital inputs for controlling and monitoring system-level signals, and an I2C interface. Customers can choose from among seven Power Manager II devices to ensure device specifications meet their design requirements.

Software Support

Designs for the ispPAC-POWR6AT6 device are implemented using Lattice's Windows-based PAC-Designer® Software version 4.5. To simplify interfacing with power supplies, PAC-Designer 4.5 includes proprietary Margin and Trim support that automatically determines the correct circuit configuration for all commonly available power supply types, including discrete board-level implementations.

Pricing and Availability

Volume (10kU+) pricing for ispPAC-POWR6AT6 in a 32-pin QFN and industrial temperature range starts at $2.25. Samples are available now.

About Lattice Semiconductor

Lattice Semiconductor Corporation provides the industry's broadest range of Field Programmable Gate Arrays (FPGA) and Programmable Logic Devices (PLD), including Field Programmable System Chips (FPSC), Complex Programmable Logic Devices (CPLD), Programmable Mixed-Signal Products (ispPAC) and Programmable Digital Interconnect Devices (ispGDX®). Lattice also offers industry leading SERDES products.

Lattice is "Bringing the Best Together" with comprehensive solutions for system design, including an unequaled portfolio of non-volatile programmable devices that deliver instant-on operation, security and "single chip solution" space savings.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our third party wafer suppliers and assembly contractors, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispGDX, ispPAC, PAC-Designer and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Contact Information

    Brian Kiernan
    Corporate Communications Manager
    Lattice Semiconductor Corporation
    503-268-8739 voice
    503-268-8193 fax