SOURCE: Lattice Semiconductor Corporation

Lattice Semiconductor Corporation

May 02, 2011 03:01 ET

Lattice Announces 4 x 3.125Gbps SRIO Capability on the Mid-Range LatticeECP3 FPGA Family

Lowest Cost, Lowest Power Programmable Gen2 SRIO Solution Available

HILLSBORO, OR--(Marketwire - May 2, 2011) - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the availability of a 4 x 3.125Gbps version of the Serial RapidIO 2.1, Level 1 endpoint core utilizing the award winning LatticeECP3™ FPGA family. This is an extension of the previously announced SRIO v2.1 core that originally supported 1x and 2x up to 3.125Gbps and 4x up to 2.5Gbps. This core can be demonstrated utilizing the industry standard Lattice Advanced Mezzanine Card (AMC) form factor platform. With this announcement, Lattice demonstrates its continued leadership in mid-range FPGAs, supporting all lane configurations/rates of high speed serial protocols such as Level 1 SRIO.

"By offering an industry leading 1x, 2x and 4x up to 3.125Gbps SRIO solution on a low power, mid-range platform, our LatticeECP3 family achieves higher performance levels that have been traditionally addressed only by high end FPGAs," said Ron Warner, Vertical Marketing Manager, Wireless Infrastructure.

About the Serial RapidIO 2.1 IP Core

  • Allows for 1x, 2x and 4x lane configurations
  • Supports up to 3.125Gbps
  • Implements physical layer, transport layer, maintenance transaction handling and error management extensions
  • Provides infrastructure support for external logical layer functions, enabling maximum flexibility
  • Provides a choice of how logic layer functions interact with the rest of the system -- SoC bus or streaming interfaces
  • Supports software implementations of control plane-oriented functions such as doorbells and messages
  • Backward compatible with the v1.3 specification

For additional information about the Serial RapidIO 2.1 IP core, please visit

Pricing and Availability

The Serial RapidIO 2.1 IP core and associated AMC platform are available for immediate customer evaluation and use. For more information about licensing and pricing of the Serial RapidIO 2.1 core and the AMC, please contact your local Lattice sales office or

About the Lattice ECP3 FPGA Family

The LatticeECP3 FPGA family is comprised of the lowest power, SERDES-enabled FPGAs in the market today. The family's five FPGAs offer standards-compliant, multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are ideal for RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature fast LVDS I/O as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive video camera and display, wireline and wireless infrastructure applications.

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit Follow Lattice via Facebook, RSS and Twitter.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP3 and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Contact Information

    Brian Kiernan
    Corporate Communications Manager
    Lattice Semiconductor Corporation
    503-268-8739 voice
    503-268-8193 fax