SOURCE: Lattice Semiconductor Corporation

Lattice Semiconductor Corporation

February 23, 2009 08:00 ET

Lattice Announces New Mixed-Signal Design Software Tool Suite

PAC-Designer 5.0 Tools Support New ispClock5400D Devices, Enable Complex Power Management Designs in Smaller Power Manager ICs

HILLSBORO, OR--(Marketwire - February 23, 2009) - Lattice Semiconductor (NASDAQ: LSCC) today announced Version 5.0 of its PAC-Designer® mixed signal design tool suite with new device support and improved quality of results. The PAC-Designer 5.0 software now supports the new ispClock™5400D family of in-system programmable ICs, which are ideal for applications that require low-cost SERDES clock references and distributing high speed differential clocks.

"The PAC-Designer tool suite continues to address the needs of circuit board design engineers who need easy to use tools that optimize clock and power management designs," said Chris Fanning, Lattice Corporate Vice President and General Manager of Low Density and Mixed Signal Solutions. "Lattice's Power Manager devices enable the integration of various supply management functions such as hot-swap, sequencing, supervision and reset generation, both at lower cost and with in-system programmability. This latest release reduces the cost of implementation further by enabling smaller devices to integrate more complex power management functions."

ispClock5400D Design Support

The PAC-Designer environment makes ispClock5400D design entry and verification easy with an interactive graphical user interface schematic diagram, which provides access to all ispClock device options such as reference frequency, output buffer driver type and divider settings. Programmable analog blocks, like the FlexiClock™ I/Os and CleanClock™ PLL of the ispClock5400D device are easily modified to accommodate a variety of circuit board requirements.

Improved Quality of Results

Lattice ispPAC® Power Manager devices integrate programmable analog and PLD technologies to support digital power management solutions. The PAC-Designer 5.0 software includes an upgrade to the LogiBuilder component, which can reduce the logic consumption of PLD core macrocell resources 20-30%. LogiBuilder now supports sequencer instructions with concurrent output expressions. This instruction style can dramatically reduce the number of macrocells required to implement the embedded state machines used for intelligent power sequencing.

About the Lattice PAC-Designer Tool Suite

The PAC-Designer tool suite is the design and verification tool for Lattice ispPAC devices. The PAC-Designer software is a complete design environment, including everything needed for design, implementation, simulation and programming of supported devices.

Pricing and Availability

Lattice's PAC-Designer software for Windows is available now at no charge for download from the Lattice website,

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD and Mixed Signal programmable logic solutions. For more information, visit

Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispClock, ispLEVER, ispPAC, PAC-Designer, CleanClock, FlexiClock and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Contact Information

    Brian Kiernan
    Corporate Communications Manager
    Lattice Semiconductor Corporation
    503-268-8739 voice
    503-268-8193 fax