SOURCE: Lattice Semiconductor Corporation

Lattice Semiconductor Corporation

December 14, 2009 03:01 ET

Lattice Releases Development Platform for SERDES and Video Clock Distribution

New Evaluation Board Demonstrates Ultra-Low Jitter, Low Cost Differential Clock IC

HILLSBORO, OR--(Marketwire - December 14, 2009) - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of a $169 evaluation board for the ispClock™ 5400D programmable clock device. The new board is an easy-to-use platform for evaluating and designing with the ispClock5400D differential clock distribution device. The evaluation board can be used by itself to review the performance and in-system programmability of the 5400D device, or as a companion board and clock source for LatticeECP3™ FPGA Serial Protocol or Video Protocol evaluation boards.

Typically, expensive oscillators with LVDS or LVPECL interfaces are used as a reference clock for FPGA SERDES interface applications. The ispClock5400D device provides ultra low-jitter differential clock outputs that can be used to drive both the general purpose clocks and the SERDES reference clocks for FPGAs, ASSPs and ASICs. The evaluation board demonstrates how to interface a low-cost CMOS interface oscillator to the ispClock5400D device to produce high quality clocks for XAUI applications or 270 MHz SDI video applications.

"This new evaluation board provides an excellent development platform for differential clock implementations with the ispClock5400D device. The platform provides a way to interface rapidly to bench test equipment to confirm the low period and phase jitter performance of the 5400D family," said Shyam Chandra, Lattice's Product Manager for Mixed Signal Devices. "Traditional clock distribution ICs do not help with timing challenges in a circuit board; in fact, in many cases fixing timing problems requires new circuit board layout and fabrication. Our new evaluation board showcases the skew control flexibility of the ispClock5400D device, which costs far less than traditional clock distribution ICs."

About the ispClock5400D Evaluation Board

The ispClock5400D evaluation board is a versatile, ready to use hardware development platform for evaluating and designing with ispClock programmable clock devices. The platform is based on a 6" x 4" evaluation board that features the ispClock 5406D device in a lead-free 48-pin QFNS package, SMA connectors and crystal oscillator circuits, as well as expansion headers for JTAG, I2C bus and test. The kit includes a preconfigured ispClock5400D demonstration design that illustrates the low-jitter performance and time/phase skew output control of the device. The board is controlled with switches and push buttons. A pin header provides access to the I2C bus interface of the ispClock5406D device.

Users may extend or modify the preconfigured demo using PAC-Designer® and ispVM™ software. PAC-Designer design software for the ispClock family can be downloaded free from the Lattice website,

Pricing and Availability

Pricing for the ispClock5400D evaluation board is $169. The boards are available for immediate ordering via the Lattice online store at and through select authorized Lattice distributors at All ispClock5400D and LatticeECP3 devices are fully production qualified and available now for volume shipments.

More information regarding the ispClock5400D evaluation board is available at

About ispClock Programmable Clock Devices

The ispClock5400D device family features in-system programmable differential clock distribution with fully programmable features that allow users to program in different frequencies based on dividers and PLL functions. Additional value is added with multiple differential I/O support for various standards while maintaining the low-jitter required for high performance systems. The ispClock5400D family supports differential output drivers for programmable differential input reference/feedback standards: LVDS, LVPECL, HSTL, SSTL and HCSL. Included on-chip are programmable termination and a clock A/B selection multiplexer, programmable time skew, programmable phase skew and various programmable output enable features. Through I2C the user has access to nearly all the programmable features of the ispClock5400D.

The ispClock5400D maintains extremely low-jitter:

--  Ultra low cycle-to-cycle jitter (29ps p-p)
--  Ultra low period jitter (2.5ps)
--  Low output-to-output skew ( < 75ps)

For more information about the Lattice ispClock device family, visit

About LatticeECP3 FPGAs

The low power, high value, third generation LatticeECP3 family offers the industry's lowest power consumption and price of any SERDES-capable FPGA devices. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. For more information about the LatticeECP3 FPGA family, visit

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit

Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP3, ispClock, PAC-Designer, ispVM and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Contact Information

    Brian Kiernan
    Corporate Communications Manager
    Lattice Semiconductor Corporation
    503-268-8739 voice
    503-268-8193 fax