SOURCE: Lattice Semiconductor Corporation

Lattice Semiconductor Corporation

March 30, 2011 03:01 ET

Lattice Semiconductor to Showcase Latest Low Cost, Low Power Design Solutions at FPGA Camp

Lattice Will Demonstrate How the LatticeECP3 FPGA Family Provides Low Cost Image Processing and How the MachXO2 PLD Family Can Reduce Power Below 20uW

HILLSBORO, OR--(Marketwire - March 30, 2011) - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that it is participating in FPGA Camp, April 6th in Santa Clara, California. Lattice is both a sponsor and participant in this design community-organized event. Lattice will participate in the panel discussion, "State of FPGAs - Current and Future," and also provide demonstrations highlighting the latest applications enabled by their recently announced MachXO2™ PLD and LatticeECP3™ FPGA technologies.

"We are proud to sponsor and participate in FPGA Camp," said Doug Hunter, Lattice Vice President of Corporate Marketing. "The Open Source nature of this event fits well with Lattice's culture of innovation and openness. We look forward to sharing our programmable solutions with the designers attending FPGA Camp."

About the Lattice MachXO2 PLD Family
Lattice MachXO2 devices provide embedded designers an unprecedented mix of low cost, low power and high system integration. The MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory, more than a 100X reduction in static power and up to 30% lower cost compared to the prior generation MachXO PLD family. These devices are ideally suited for the most popular functions used in embedded system applications (telecom infrastructure, computing, high-end industrial, high end-medical) and embedded consumer applications (digital TVs, smart phones, GPS devices, mobile computing, digital cameras). For more information about the MachXO2 PLD family, visit

About the Lattice ECP3 FPGA Family
The LatticeECP3 FPGA family is comprised of the lowest power, SERDES-enabled FPGAs in the market today. The family's five FPGAs offer standards-compliant, multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are ideal for RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature fast LVDS I/O as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive video camera and display, wireline and wireless infrastructure applications. For more information about the LatticeECP3 FPGA family, visit

About FPGA Camp
FPGA Camp is a conference that brings together engineers to discuss FPGA technology, applications, methodologies, best practices and challenges. FPGA Camp also provides a forum for designers to meet other designers to share their experiences. Since its inception in 2009, FPGA Camp has remained vendor neutral. Attendance and participation are free, and as a result industry participants refer to FPGA Camp as an Open Source conference.

FPGA Camp is being held April 6th in Santa Clara, CA. Details and registration can be found at

About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit
Follow Lattice via Facebook, RSS and Twitter.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), MachXO, LatticeECP3 and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Contact Information

    Brian Kiernan
    Corporate Communications Manager
    Lattice Semiconductor Corporation
    503-268-8739 voice
    503-268-8193 fax