SOURCE: Lattice Semiconductor Corporation

Lattice Semiconductor Corporation

September 14, 2009 03:01 ET

LatticeECP3 FPGA Family, ProcessorPM Power Management IC Are Finalists in EDN China Innovation Awards Competition

Lattice Products Are Chosen From Among Record Number of Entries

HILLSBORO, OR--(Marketwire - September 14, 2009) - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that a panel of industry experts has named the LatticeECP3™ FPGA family and the mixed-signal ProcessorPM™ power management device as finalists in EDN China's prestigious Innovation Awards competition. The ECP3 family is competing in the "Programmable Logic" category, and the ProcessorPM device is a finalist in the "Power Device and Module" category.

"Despite the current financial crisis and economic slowdown in the electronics industry, innovation has not been hampered," said EDN China editor Jeff Lu. "In fact, for this year's Innovation Awards, we received over 95 companies' nominations with nearly 200 innovative products. The finalists have been chosen according to the stringent criteria set by the panel of distinguished judges."

The EDN China Innovation Awards recognize innovation that has led to technology or product advancements. Voting for the Awards winners takes place through September 21 at http://award.ednchina.com. Winners will be announced in November at a ceremony in Shenzhen, China.

"We are very pleased and excited that two of our product families have been selected by the EDN China Innovation Awards judges," said Doug Hunter, Lattice's Vice President of Corporate Marketing. "Our mid-range, SERDES-capable ECP3 FPGAs solve the power problems faced by designers of complex systems, and our ProcessorPM device addresses the power management challenges presented by a system design with an advanced processor on the board."

About the LatticeECP3 FPGA Family

The LatticeECP3 family defines a new mid-range, value-based class of FPGAs, not only by further reducing costs, but also by reducing static power consumption by up to 80% and total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs. By making careful design choices and minimizing die size, Lattice can offer designers the benefits of high speed serial I/O and processing capabilities, without the power and cost premiums typically associated with these types of devices.

About the ProcessorPM Power Manager

Lattice brings the benefits of programmability to power management with the ProcessorPM device, a programmable, single chip power management solution for the reset generation, watchdog timer and voltage supervision functions found in virtually every microprocessor or DSP design. The ProcessorPM device reduces customers' costs by integrating functionality typically implemented using individual reset, supervisor and watchdog ICs. While priced competitively with off-the-shelf three-supply supervisor ICs, the ProcessorPM device integrates the functions of reset generator ICs with variable pulse stretch timing, watchdog timer ICs running up to two minutes, and six-supply supervisor ICs.

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com


Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP3, ProcessorPM and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Contact Information

  • EDITORIAL/READER CONTACT:
    Brian Kiernan
    Corporate Communications Manager
    Lattice Semiconductor Corporation
    503-268-8739 voice
    503-268-8193 fax
    brian.kiernan@latticesemi.com