SOURCE: Verific Design Automation

February 11, 2015 11:00 ET

Longtime Verific Customer Rocketick Renews Parser Platform License

SystemVerilog Parser Platform Serves as Front End to RocketSim Simulation Accelerator

ALAMEDA, CA--(Marketwired - Feb 11, 2015) - Verific Design Automation, provider of SystemVerilog, VHDL and UPF parsers, today announced Rocketick Technologies Ltd., a leading provider of Verilog simulation acceleration solutions for chip verification, has renewed its license for Verific's SystemVerilog Parser Platform.

Rocketick, a Verific customer since 2009, uses Verific's SystemVerilog Parser Platform as the front end to RocketSim™, a multi-core processor-based accelerator used on a wide range of Verilog simulations to solve functional verification bottlenecks. RocketSim can accelerate simulations of large designs by 5-10X.

"Partnerships with customers such as Rocketick are important to us because they can give us feedback on large RTL designs in the semiconductor space," notes Rob Dekker, Verific's founder and chief technology officer. "Jointly, we have worked on SystemVerilog designs in access of 25-million lines of RTL code, distributed over thousands of files."

"Verific has been an outstanding partner," adds Uri Tal, Rocketick's chief executive officer. "Its software is high quality, as is the support and service. I can't think of a more responsive and supportive EDA vendor."

Verific's software is used as the front end to a wide range of electronic design automation (EDA) and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Its Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl application programming interfaces (APIs). Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

At DVCon
Rocketick and Verific will exhibit at DVCon Monday, March 2, from 5-7 p.m. and Tuesday and Wednesday, March 3 and 4, from 2:30-6 p.m. at the Doubletree Hotel in San Jose, Calif., in booths #305 and #802, respectively.

More information about DVCon can be found at: http://dvcon.org/

About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog, VHDL and UPF. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: info@verific.com. Website: www.verific.com.

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Contact Information

  • For more information, contact:
    Nanette Collins
    Public Relations for Verific
    (617) 437-1822
    Email Contact