SOURCE: Verific Design Automation

April 19, 2016 11:00 ET

Longtime Verific Customer S2C Upgrades to SystemVerilog

SystemVerilog Parser Integrated with Prodigy Prototyping Platform

ALAMEDA, CA--(Marketwired - Apr 19, 2016) - Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF parsers used throughout the semiconductor industry, announced today S2C, Inc., a leading provider of FPGA-based rapid prototyping solutions, licensed its SystemVerilog parser.

A longtime customer of Verific's Verilog and VHDL parsers, S2C upgraded to Verific's SystemVerilog parser and will integrate it into Prodigy, its rapid prototyping platform for exploring, navigating, analyzing, documenting and modifying large designs. S2C will license the software as source code, and will have access to Verific's comprehensive support and maintenance.

"Verific continues to provide the best SystemVerilog and VHDL parsers in the EDA industry," says Mon-Ren Chene, chief technology officer of S2C. "We have had a long and valued partnership with Verific and it was reinforced by its strong support as we begin using SystemVerilog."

Verific's SystemVerilog, VHDL and UPF parsers are in production and development flows throughout electronics companies worldwide, from emerging companies such as S2C to established Fortune 500 semiconductor vendors. Applications range from analysis, simulation, formal verification and synthesis to emulation and virtual prototyping, in-circuit debug and design-for-test. The software is distributed as C++ source code with C++, Python and Perl application programming interfaces (APIs) and compiles on all 32- and 64-bit Unix, Linux, Windows and Mac operating systems.

"We've had the pleasure of working with S2C for close to 10 years, watching it grow and expand its product offerings," remarks Michiel Ligthart, Verific's president and chief operating officer. "We look forward to an ongoing and mutually beneficial partnership."

Verific will demonstrate its SystemVerilog, VHDL, and UPF parsers in Booth #538 during the Design Automation Conference (DAC), as will 13 exhibitors who chose Verific's tools as the front end for a variety of verification software and hardware applications. Verific invites attendees to stop by its booth to learn more and to pick up this year's giraffe giveaway.

DAC will be held June 5-9 between10 a.m. and 6 p.m. at the Austin Convention Center in Austin, Texas. To schedule a demonstration, contact Rick Carlson, Verific's vice president of sales. He can be reached at (970) 946-1755 or via email at rick@verific.com or visit Verific's website located at: http://www.verific.com

About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog, VHDL and UPF. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: info@verific.com Website: www.verific.com

Verific Design Automation and Tortuga Logic acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

Contact Information

  • For more information, contact:
    Nanette Collins
    Public Relations for Verific
    (617) 437-1822
    Email Contact