SOURCE: Maxim Integrated Products

September 04, 2007 13:07 ET

Maxim's Telecom Timing IC Enables 1G and 10G Synchronous Ethernet, Supports SONET/SDH, PDH, and Wireless Systems

SUNNYVALE, CA--(Marketwire - September 4, 2007) - Maxim Integrated Products (NASDAQ: MXIM) introduces the DS3104, a new telecom timing device that enables 1G and 10G synchronous Ethernet and supports SONET/SDH, PDH, and wireless systems.

Synopsis for Investor:

* Applications include line cards and other subsystems in a wide variety
  of wireline and wireless systems, including ADMs, digital cross-connects,
  carrier-class switches and routers, wireless base stations, DSLAMs and
  multiservice access nodes.
* Maxim has applied its proven DSP-based digital PLL (DPLL) technology in
  this new line-card timing IC for next-generation telecom systems.
* This is the first IC in the industry to provide full carrier-class clock
  synchronization support for new SyncE line cards and mixed
  SONET/SDH/SyncE line cards.
* The DS3104 meets the performance specifications defined for Synchronous
  Ethernet (SyncE) by the International Telecommunication Union (ITU)
  in 2006. The new IC is already being designed in next-generation line

The new DS3104 is the industry's first timing IC to provide full carrier-class clock synchronization for new Synchronous Ethernet (SyncE) line cards and mixed SONET/SDH/SyncE line cards. Maxim has applied its proven DSP-based digital PLL (DPLL) technology, first used in the highly integrated DS3100 timing-card-on-a-chip IC, in this new line-card timing IC for next-generation telecom systems.

Key DS3104 innovations include two independent DPLLs for bidirectional frequency conversion between Ethernet clock rates and SONET/SDH rates, and complete support for all 1G, 10G, and 100M Ethernet MII clock rates. Applications include line cards and other subsystems in a wide variety of wireline and wireless systems, including ADMs, digital cross-connects, carrier-class switches and routers, wireless base stations, DSLAMs and multiservice access nodes.

The Emergence of Synchronous Ethernet

Ethernet is gradually replacing PDH and SONET/SDH links in service-provider networks. Telecom service providers are thus challenged how to carry high-quality clock synchronization over Ethernet to serve several demanding applications including wireless base stations and TDM circuit emulation (CES) equipment. One recently standardized method to address this challenge is Synchronous Ethernet (SyncE).

In SyncE, Ethernet links are synchronized by timing their bit clocks from high-quality, stratum-1-traceable clock signals in exactly the same manner as SONET/SDH. In 2006 the International Telecommunication Union (ITU) outlined the SyncE concept in its Recommendation G.8261. In June 2007, the ITU standardized SyncE performance requirements in a new Recommendation called G.8262.

"The DS3104 is in high demand at telecom equipment manufacturers," stated Michael Smith, Managing Director of the Company's Communications Business Unit. "Major telecom service providers have urged the ITU to quickly standardize SyncE performance requirements, so they can plan the network synchronization aspects of their next-generation networks," Smith explained. With the ITU's SyncE performance requirements standardized this year, telecom equipment manufacturers have started numerous SyncE line-card designs for a variety of equipment types in anticipation of service providers' demand. "The DS3104 has already been selected as the line-card timing IC for several of these new line cards," Smith added.

Architectural Overview

The DS3104 continually monitors up to eight input clocks. Built-in reference-selection logic automatically chooses the highest priority, valid input clock for each of the two DPLLs.

The main DPLL typically takes system clocks (e.g., 19.44MHz) from dual redundant timing cards, monitors both, selects one to which to lock, and synthesizes various clocks needed on the line card (e.g., 125MHz for 1G SyncE transmitters). This main DPLL also provides the hitless switching and holdover capabilities needed on the line card. The second DPLL is typically used to convert recovered line clocks (e.g., 125MHz from 1G SyncE receivers) to suitable backplane line clocks (e.g., 19.44MHz), which are sent to the two system timing cards. Each DPLL is followed by a clock-multiplying, jitter-attenuating APLL and dividers that can provide a wide array of clock rates to the seven output clocks.

Technical Details

The DS3104 has very flexible clock I/O capabilities. Eight clock inputs are available, and each can be assigned to either of the two internal DPLLs. Inputs are continually monitored for quality and can be automatically qualified and disqualified by the device according to configurable criteria. Four clock inputs are CMOS/TTL; the other four are LVDS/LVPECL or CMOS/TTL. The eight clock inputs accept all common telecom clock rates including 2kHz, 8kHz, DS1, E1, DS2, DS3, E3, OC-3, and Nx19.44MHz, and all Ethernet MII clock rates including 25MHz, 125MHz, and 156.25MHz. The clock inputs also accept all multiples of 2kHz up to 77.76MHz and all multiples of 8kHz up through 155.52MHz, making the inputs compatible with a variety of other industry clock rates including 13MHz and 30.72MHz base-station clocks and 10MHz from GPS receivers.

The DPLLs in the DS3104 can direct-lock to a number of common telecom frequencies. The DPLLs can also lock to integer multiples of the direct-lock frequencies by using programmable input dividers. DPLL bandwidths are programmable from 1Hz to 600Hz, and a variety of damping factors are available. The main DPLL can optionally use phase build-out techniques to perform hitless switching to the secondary system clock when the primary system clock fails. Typical output-clock phase movement in this scenario is less than one nanosecond, even when the device is clocked by an inexpensive crystal oscillator that is not temperature-compensated. The main DPLL also has a precise digital holdover mode to maintain output clocks in case both system clock references fail or are unavailable.

The DS3104 can produce a total of seven output-clock frequencies simultaneously, plus 2kHz and 8kHz frame pulses. Each output clock can be frequency-locked to either of the two DPLLs for maximum flexibility. For combination SONET/SDH/SyncE line cards, the device can simultaneously produce SONET/SDH rates (e.g., 155.52MHz), the 1G Ethernet GMII clock rate (125MHz), and the 10G Ethernet XGMII clock rate (156.25MHz or 312.5MHz). All rates are frequency-locked to the selected system clock through the main DPLL. Of the seven output clocks, three are CMOS/TTL, two are LVDS/LVPECL, and two are dual CMOS/TTL and LVDS/LVPECL. The output clocks have the same frequency options as the input clocks, plus differential-signal rates as high as 312.5MHz. In addition, programmable synthesis engines can produce any multiple of 2kHz up to 77.76MHz, any multiple of 8kHz up to 311.04MHz, and many other frequencies as needed.

Package, Pricing and Availability

The DS3104 is available now. The device has an SPI™ serial bus interface and is packaged in an 81-lead, 10mm x 10mm BGA. Both 5/6- and full-RoHS-compliant package options are available. The device operates over the full industrial temperature range of -40 degrees Celsius to +85 degrees Celsius. The DS3104DK demo kit is available for device evaluation. For more information please visit:

SPI is a trademark of Motorola, Inc.

DATA SHEET: A Data Sheet for this product is available on the web.

GRAPHIC: The graphic for this product is available on the web in three formats:

PREVIEW image (smaller image to view in Navigator or Explorer):

JPEG (300 dpi, high quality, RGB color)

TIFF (300 dpi uncompressed CMYK TIF, in a .ZIP archive*)

(* Use Winzip, StuffIt Expander or similar de-archive utility to access the .ZIP file)

Contact Information

  • Editors' Contact:
    Drew Ehrlich
    Public Relations

    Readers' Contact:
    Customer Service