SOURCE: SuVolta, Inc.

SuVolta, Inc.

August 17, 2012 15:37 ET

Media Alert: SuVolta Joins Semiconductor Industry Leaders to Discuss Advances in IC Design at Hot Chips 24

Conference Features Real Products and Realizable Technology for Microprocessors, SOCs, Multimedia and Imaging ICs, and More

LAS GATOS, CA--(Marketwire - Aug 17, 2012) -

On August 29, 2012, Dr. Robert Rogenmoser, SuVolta's SVP of product development and engineering, will join industry experts at Hot Chips 24: A Symposium on High Performance Chips. Presenters will discuss approaches to taming IC power consumption while scaling to advanced process nodes and the benefits of low-power circuit design.

Controlling power consumption is the greatest challenge for chip designers. In his presentation, titled "Reducing Transistor Variability For High Performance Low Power Chips," Dr. Rogenmoser will discuss the negative impact of high transistor variability on power and performance, its effects on energy efficiency, and how SuVolta's Deeply Depleted Channel (DDC) technology, can be leveraged using circuit design techniques to significantly lower power consumption in high performance chips.

The semiconductor industry is being driven by consumers' insatiable demand for smaller, less expensive and higher performance mobile devices. For the ever-growing mobile market, reducing power consumption and controlling cost are key. However, the process technology used by the semiconductor industry for the past 40 years -- conventional bulk planar CMOS -- is hitting active and leakage power limits, and voltage scaling has stagnated at ~1 Volt for the past 10 years. One major implication of this barrier is manifested in the semiconductor industry's constant struggle to reduce power consumption and increase battery life of mobile devices without sacrificing performance or cost.

SuVolta's DDC transistor technology and DDC-optimized circuits and design techniques enables scaling (reduction) of two of the most critical transistor parameters -- scaling of supply voltage, and scaling of transistor size to the sub-20nm node and smaller. The DDC technology is a component of the PowerShrink™ platform which applies across a wide range of integrated circuit (IC) products, including processors, SRAMs, and SOCs that are critical to today's mobile products.

Representatives from Altera Corporation, Intel Corporation and SuVolta, Inc. will present during the "Technology and Scalability" session.

The Flint Center for the Performing Arts, Cupertino, California, USA

August 29, 2012, 8:45 a.m. - 10:15 a.m., "Technology and Scalability" session

Register online at

Contact Information

  • Contacts:
    Margo Westfall
    SuVolta, Inc.
    +1 (408) 429-6058
    Email Contact

    Vishal Bali
    The Hoffman Agency
    +1 (408) 975-3087
    Email Contact