October 24, 2006 14:11 ET

NEC Improves Product Quality; Lowers Manufacturing Costs With Cadence Encounter Test

Encounter True-Time Test Reduces Test Escapes and Improves Customer Satisfaction by Shortening Time to High-Volume Manufacturing

SAN JOSE, CA -- (MARKET WIRE) -- October 24, 2006 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced NEC Corporation is adopting the Cadence® Encounter® Test products to improve the testability and quality of complex devices used in high-end computers developed by the NEC Computers Division. This was made possible by the deployment of Encounter True-Time Test, which identifies small delay defects, commonly present in devices manufactured using advanced process technology and often not detectable with existing test methodologies.

For NEC, improvements in testability and the resulting enhanced quality of their devices translate directly into reduced manufacturing costs and lead time helping NEC satisfy their customers. This is essential for NEC, which develops some of the world's highest performing supercomputers, highly reliable mainframe products and open servers for a demanding and ever changing market environment.

Encounter True-Time Test technology reduces test escapes which impact product quality. Test escapes, measured in defects per million (DPM), are defined as defective devices passing required tests during specific points in the manufacturing process (wafer probe, package test, burn-in, etc.), but failing later in the manufacturing chain. These test escapes result in increased costs and lead time for manufacturing products. To reduce test escapes, Encounter True-Time Test's Timing-Aware ATPG approach tests each potential fault with the tightest possible timing. The results are highly effective tests that can significantly reduce DPM relative to traditional delay tests.

"In our high-end products, high-quality LSI devices are mandatory in order to reduce costs for material procurement and manufacturing as well to reduce lead time for mass-production. It is a fundamental requirement for our NEC Computers Division to lower DPM by reducing test escapes," said Takayuki Noguchi, General Manager Computers Division, NEC Corporation. "We are extremely pleased with Encounter Test's ability to improve the quality of our manufacturing methodology. Encounter True-Time Test has markedly improved our production effectiveness."

Given NEC's positive results with Encounter True-Time Test, NEC is planning to also adopt Encounter Test compression and Encounter Diagnostics -- all key components of the Encounter digital IC design platform. Encounter Test compression addresses the escalating cost of manufacturing high-quality silicon with a choice of XOR or MISR compression architectures. The MISR architecture enables superior test-time reduction, while the XOR architecture enables a single-pass diagnostics methodology for newer yield-limited products. Encounter Diagnostics accelerates yield ramp with its volume and precision modes and its physical-aware diagnostic capabilities -- localization of physical structures within the design that cause yield loss.

"We are delighted to contribute to the quality improvements of NEC's advanced LSI designs," said Sanjiv Taneja, vice president of R&D for Encounter Test at Cadence. "Once again, a key customer has validated Encounter Test's unparalleled ability to detect the small delay defects prevalent in leading-edge process technologies. We look forward to bringing the full breadth and depth of Encounter Test to NEC enabling them to achieve higher quality, lower cost and faster yield ramp of their devices."

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence, the Cadence logo and Encounter are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Contact Information

  • For more information, please contact:

    Michael Fournell
    Cadence Design Systems, Inc.