SOURCE: NetSpeed Systems

NetSpeed Systems

September 29, 2016 10:44 ET

NetSpeed Releases Gemini 3.0 Cache-Coherent NoC IP to Supercharge Heterogeneous SoC Designs

SAN JOSE, CA--(Marketwired - September 29, 2016) - NetSpeed Systems Inc., announced today the release of its Gemini 3.0 cache-coherent network-on-chip IP that maximizes the performance of heterogeneous multicore system-on-chip (SoC) designs for cloud computing, automotive, mobile and IoT applications.

Many of today's applications build in human-like comprehension and decision-making capabilities. Applications such as Advanced Driver Assistance Systems (ADAS) offer users an augmented experience of the physical, real-world environment and include computer-generated sensory input such as sound, video, graphics or GPS data. The technologies underlying these applications, such as computer vision, facial recognition, voice recognition and other machine learning based capabilities require far more processing performance and much better power efficiency than is attainable with traditional multicore processor platforms.

"Processors are becoming increasingly specialized to meet the needs of their target applications," said Linley Gwennap, principal analyst at the Linley Group. "To satisfy complex application requirements, many SoCs now include a mix of CPU cores, computing clusters, GPUs and other computing resources and specialized accelerators. To maximize the performance of these heterogeneous designs, SoCs need a robust on-chip-network such as Gemini that optimizes the communication among the various components and arbitrates the sharing of memory and other critical resources."

"Gemini 3.0 is a next generation system-on-chip (SoC) interconnect platform that specifically addresses the complexities and the opportunities of heterogeneous system architectures," said Anush Mohandass, vice president of marketing and business development at NetSpeed. "Gemini enables SoC architects to implement designs that can achieve more than 10x greater performance in a reasonable power envelope. This is something that is not feasible with traditional multicore designs."

"When designing an SoC, the conventional approach is to architect the system with its IP blocks and interconnect and simulate it later in the development process when most of the design decisions have been made," said Fred Weber, former AMD CTO and industry veteran who is a member of NetSpeed's board. "This is essentially a trial and error approach that is expensive, time-consuming and risky. Gemini, on the other hand, enables system architects to perform modelling and simulation much early in development before integration begins. NetSpeed's machine learning capabilities rapidly explore a multitude of models and architecture options to give system architects accurate system level performance predictions right from the beginning."

Gemini is the only SoC interconnect solution that uses machine learning to accurately model the system as whole to achieve the best application performance. In contrast, conventional approaches tend to optimize individual subsystems in isolation, which can result in bottlenecks and systems that are overdesigned to handle worst case conditions. Gemini uses advanced networking algorithms to rapidly create a cache-coherent SoC interconnect that is deadlock-free and delivers quality of service (QoS) for all use cases. It offers OEMs an easier and more cost effective way to assemble robust heterogeneous SoCs that provide the performance necessary for rich and complex applications.

Gemini 3.0 offers unprecedented configurability allowing users to customize every component of the interconnect from IP interface to routers to topology and interface links.

  • Gemini 3.0 is first and only solution to support both the ARM ® AMBA® 5 CHI (Coherent Hub Interface) and ARM® AMBA® 4 AXI Coherency Extensions (ACE) on-chip interconnect standards in a single design and includes support for broadcast and multicast which can dramatically improve performance.
  • It supports up to 64 fully cache-coherent CPU clusters, GPU blocks and other coherent compute blocks and up 200 I/O coherent and non-coherent agents.
  • It can handle cache-coherent, I/O-coherent, and non-coherent traffic in a single SoC interconnect design platform.
  • It offers unique system level optimizations including integrated DMA, on-chip RAM and Last Level Cache (LLC) IPs with runtime configurability.

Supporting Quotes:

ARM:
"We are committed to bringing a variety of competitive options to our partners through our strong ecosystem and NetSpeed's Gemini 3.0 is one more example of this approach," said Ian Ferguson, vice president of worldwide marketing and strategic alliances. "NetSpeed's Gemini cache-coherent interconnect, with support for ARM® AMBA® 4 AXI Coherency Extensions (ACE) and AMBA 5 Coherent Hub Interface (CHI) standards, will enable the development of heterogeneous SoC platforms."

Cadence Design Systems:
"Cache coherency is becoming an integral part of heterogeneous system architectures in next generation SoC designs and it is exciting to see an ecosystem partner like NetSpeed continue bringing innovative solutions to market" said Nimish Modi, Sr. VP, Marketing & Business Development at Cadence Design Systems. "The integration of solutions such as Gemini 3.0 with Cadence's comprehensive tool and design IP solutions enables SoC architects and designers to optimize performance, while getting their designs to market much faster."

Imagination Technologies:
"Heterogeneous processing is a key enabling technology for a wide range of applications and Imagination's IP is used extensively in heterogeneous SoCs," said James Aldis, Architect at Imagination Technologies and a key contributor to the Heterogeneous System Architecture (HSA) Foundation. "In today's sophisticated multi-core, multi-cluster SoC designs, chip designers face a tremendously complex task in integrating and interconnecting a wide array of IP from multiple sources. NetSpeed's Gemini, which is designed to address the requirements of HSA and other emerging heterogeneous compute paradigms, simplifies this task, making integration faster and easier."

Intel Corporation:
"Ensuring design quality for highly complex SoCs is one of NetSpeed's foundational benefits," said Amir Faintuch, senior vice president and general manager of the Platform Engineering Group at Intel. "Gemini 3.0 offers SoC architects excellent configurability and programmability to embrace cache coherency while ensuring right-by-design construction."

About NetSpeed Systems
NetSpeed Systems provides scalable, coherent on-chip network IPs to SoC designers for a wide range of markets from mobile to high-performance computing and networking. NetSpeed's on-chip network platform delivers significant time-to-market advantages through a system-level approach, a high level of user-driven automation and state-of-the-art algorithms. NetSpeed Systems was founded in 2011 and is led by seasoned executives from the semiconductor and networking industries. The company is funded by top-tier investors from Silicon Valley. It is based in San Jose, California and has additional research and development facilities in Asia. For more information, visit www.netspeedsystems.com.

NetSpeed, NocStudio, NetSpeed Gemini, and the NetSpeed Systems logo are trademarks or registered trademarks of NetSpeed Systems Inc. in the United States and other countries. NetSpeed Systems and other parties may also have trademark rights in other terms used herein.

The URL for this release is located at www.netspeedsystems.com

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