SOURCE: Arteris

Arteris

May 31, 2011 08:30 ET

Network on Chip (NoC) Technology Highlighted in Peer-Reviewed Springer Journal, Design Automation for Embedded Systems

Arteris NoC Technology Implementation Used to Describe Interconnect Design Flow Best Practices and Setup of Advanced Quality of Service (QoS)

SUNNYVALE, CA--(Marketwire - May 31, 2011) - Network on chip interconnect architecture exploration and refinement are the subject of an article in the new special issue of the journal, Design Automation for Embedded Systems. The subject of this DAES special issue is, "Networks-on-Chips: Design Flows and Case Studies." The 26-page article, "Application Driven Network-on-Chip Architecture Exploration and Refinement for a Complex SoC," by authors Jean-Jacques Lecler and Gilles Baillieu, both of Arteris Inc., explains the design flow for creating, simulating and verifying a network on chip interconnect and explores through detailed examples how rate adaptation, quality of service, and timing closure are achieved using network on chip technology.

The article can be downloaded for free from the Arteris website.

"The authors provide good insights into how NoCs can be generated for real SoC designs using Arteris' state-of-the-art industrial work flow," said Kees Goossens, Electronic Systems Group, Faculty of Electrical Engineering, Eindhoven University of Technology, The Netherlands.

This article presents an overview of the design process of a NoC interconnect, using Arteris technology. It summarizes the various features a NoC is required to implement to be integrated in modern SoCs and describes a top-down approach development approach, based on the progressive refinement of the NoC description, from its functional specification to its verification. The approach is illustrated by a typical use-case of a NoC embedded in a hand-held gaming device system on chip. The methodology relies on the definition of the performance behavior and expectations, which can be early and efficiently simulated against various NoC architectures. The system architect is then able to identify bottle-necks and converge towards the NoC implementation fulfilling the requirements of the target application.

"The selection of Arteris for this peer-reviewed article is further proof of Arteris' commitment to deliver interconnect IP and tool technologies on a continuous basis to solve mainstream SoC interconnect issues," said K. Charles Janac, President and CEO of Arteris. "The ability of our network on chip technology to more easily fulfill the requirements of modern systems on chip is making it the gold standard for on-chip interconnects."

About Arteris

Arteris, Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. Results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster development of ICs, SoCs and FPGAs.

Founded by networking experts, Arteris operates globally with headquarters in San Jose, California and an engineering center in Paris, France. Arteris is a private company backed by a group of international investors including ARM Holdings, Crescendo Ventures, DoCoMo Capital, Qualcomm Incorporated, Synopsys, TVM Capital, and Ventech. More information can be found at www.arteris.com.

Contact Information

  • For more Arteris information, contact:
    Kurt Shuler
    Arteris, Inc.
    +1 408-470-7300
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    Mike Sottak
    Wired Island, Ltd.
    +1 408-876-4418
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