SOURCE: Lattice Semiconductor Corporation

Lattice Semiconductor Corporation

April 27, 2009 08:00 ET

New Lattice "Processor Power Manager" Reduces the Cost of Microprocessor Support

Integrates the Functions of Separate Power Management ICs Used in Microprocessor and DSP Designs; Improved Monitoring Accuracy Increases Design Reliability

HILLSBORO, OR--(Marketwire - April 27, 2009) - Lattice Semiconductor (NASDAQ: LSCC) today announced a new member of its award-winning Power Manager II family, the ProcessorPM™ device, a programmable, single chip solution for the reset generation, watchdog timer and voltage supervision functions found in virtually every microprocessor or DSP design. While priced competitively with off-the-shelf three-supply supervisor ICs, the ProcessorPM device integrates the functions of reset generator ICs with variable pulse stretch timing, watchdog timer ICs running up to two minutes, and six-supply supervisor ICs.

"The ProcessorPM device reduces our customers' costs by integrating functionality typically implemented using individual reset, supervisor and watchdog ICs," said Chris Fanning, Corporate Vice President and General Manager of Low Density and Mixed Signal Solutions. "The ProcessorPM device also provides our customers with greater design flexibility by incorporating Lattice's in-system programmability."

The ProcessorPM device provides six programmable threshold comparators (accuracy -0.7 %) with individual glitch filters to monitor up to six supply rails without using external resistors and capacitors. The comparator outputs are connected to a 16 macrocell, ruggedized on-chip PLD (programmable logic device) that generates the reset and brownout signals by using simple logic equations. Four timers can be individually programmed from 32 microseconds to 2 seconds and used for implementing watchdog timers or for reset pulse stretching. Two digital inputs can be used for manual reset inputs or for monitoring other digital inputs such as Power Down or Disable Processor signals.

All device settings are stored using on-chip non-volatile EEPROM that is programmed via a JTAG interface. Design modifications after the board is assembled, such as changing thresholds or altering timer values, can be achieved easily by modifying the design in PAC-Designer® software and then downloading it into the design through JTAG. There is no need to change any resistors or capacitors.

Factory Preprogrammed ProcessorPM Increases Convenience and Reduces Board Cost

ProcessorPM devices are preprogrammed with an initial configuration to integrate a programmable six-supply reset generator (configured through pin strapping) and a programmable watchdog timer (configured through pin strapping). This configuration can be used as is across a large number of designs. The original configuration software source code is also provided to enable integration of additional functions for further board cost reduction.

ProcessorPM Design Support

ProcessorPM designs can be implemented using the intuitive, user-friendly GUI provided in version 5.1 of the PAC-Designer software tool suite, which can be downloaded for free from the Lattice website, www.latticesemi.com/pac-designer.

PAC-Designer 5.1 software's enhanced LogiBuilder capability enables designers to reduce their solution cost. The LogiBuilder requires 20-30% less PLD logic, enabling further integration of microprocessor support functions into the ProcessorPM device.

The ProcessorPM device can be customized for a given design environment in four simple steps. The first step is to set up the monitoring thresholds. Using a simple pull down menu, the supply fault detection thresholds for a given design can be set using 192 threshold steps for each of the voltage monitoring inputs. The second step is to configure the logic equation and timer delay setting to meet the reset pulse stretching, output polarity and selected supply monitoring using the intuitive LogiBuilder interface. The third step is to iterate through the design using the waveform simulator. The final step is hardware verification: downloading the design into a Processor Power Manager evaluation board and verifying the design in hardware before using it in schematic.

Pricing and Availability

Samples of the ProcessorPM (24-pin QFNS package) device are available now. The ProcessorPM device is priced at $0.75 in 200K piece volumes.

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD and Mixed Signal programmable logic solutions. For more information, visit www.latticesemi.com

Lattice Semiconductor Corporation, Lattice (& design), L (& design), ProcessorPM, PAC-Designer, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

Contact Information

  • EDITORIAL/READER CONTACT:
    Brian Kiernan
    Corporate Communications Manager
    Lattice Semiconductor Corporation
    503-268-8739 voice
    503-268-8193 fax
    brian.kiernan@latticesemi.com