SOURCE: Verific Design Automation

January 20, 2011 10:00 ET

NextOp Software Selects Verific Design Automation SystemVerilog

Integrates Assertion-Based Verification Solutions With SystemVerilog Parser, Elaborators

ALAMEDA, CA--(Marketwire - January 20, 2011) - Verific Design Automation today said that NextOp Software, Inc. has licensed its software for use with the NextOp assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability.

NextOp Software tightly integrated Verific's SystemVerilog parser and static and register transfer level (RTL) elaborators with BugScope assertion synthesis, a tool that synthesizes high-quality assertions and functional coverage properties from the RTL design and testbench.

"Verific's SystemVerilog solution was referred to us by one of our key strategic accounts," notes Yunshan Zhu, NextOp Software's president and chief executive officer. "We have been impressed with Verific's SystemVerilog solution and its technical support team. Our assertion technology requires extensive language elaboration, all of which Verific fully supports."

Since its founding in 1999, Verific's parsers and elaborators have become the industry's de facto standard. In addition to NextOp Software, its software serves as the front end to a wide range of Electronic Design Automation (EDA) and Field Programmable Gate Array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of RTL designs. Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux, and Windows operating systems.

Concludes Michiel Ligthart, Verific's chief operating officer: "NextOp Software is a great example of the creativity and ingenuity alive and well in EDA. It's been a pleasure to work with its development team."

About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end software supporting SystemVerilog, Verilog and VHDL design. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: www.verific.com.

NextOp Software and Verific Design Automation acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

Contact Information

  • For more information, contact:
    Nanette Collins
    Public Relations for Verific
    (617) 437-1822
    Email Contact