SOURCE: Real Intent

Real Intent, formal verification, EDA, Electronic Design Automation, ASIC, FPGA

January 13, 2010 14:43 ET

Prakash Narain, Real Intent's CEO, Presents Seminar on the Benefits of Formal Technology for Electronic Design Verification at 2010 EDSFair, Yokohama, Japan

YOKOHAMA, JAPAN--(Marketwire - January 13, 2010) -


Prakash Narain, President and CEO of Real Intent Inc., is presenting at the Electronic Design and Solution Fair (EDSFair 2010) in Yokohama, Japan, on the topic of Automatic Formal Verification Technology for Electronic Design.


Seminar Title: Formal Technology for Verification


The seminar will focus on Formal Verification technology and its cost effective application in design flows. Verification spans functionality to implementation and often, implementation requirements drive functionality modifications causing functional failures. Incremental verification with cost effective application of formal analysis is the best opportunity to improve design flows.

Thursday, January 28, 2010
15:30 to 16:15 pm
Pacifico, Yokohama, Japan

Information and Registration

For more information and to register for EDSFair, please visit or

To schedule a meeting or demonstration, please email or For more information about Real Intent and its verification product families, please visit

About Real Intent

Real Intent is the innovator in automating the intelligence of formal techniques for design verification. This technology is being used to solve critical problems encountered by electronic design and verification teams worldwide. Real Intent's family of products dramatically improves the functional verification efficiency of leading edge ASIC and FPGA devices.

Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: +1 (408) 830-0700 fax: +1 (408) 737-1962, Web:, e-mail:, Twitter:

Contact Information