SOURCE: Lattice Semiconductor Corporation

Lattice Semiconductor Corporation

April 05, 2011 03:01 ET

Programmable Logic Innovations for Consumer and System Designers to Be Showcased in Lattice Semiconductor's 2011 Seminar Series

HILLSBORO, OR--(Marketwire - April 5, 2011) - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced plans for its 2011 Programmable Logic Seminars. The 2011 seminars will provide designers of both consumer electronics and embedded systems rich technical and practical presentations that combine new advanced programmable logic concepts, basic design principles and real-world application examples. The seminars will feature the new MachXO2™ PLD Family, as well as the award-winning LatticeECP3™ FPGA family. MachXO2- and LatticeECP3-based evaluation kits will also be demonstrated. 

Lattice application engineers will conduct the seminars beginning in April 2011 in more than 50 cities in Asia, Europe and North America. The seminars are free, and each attendee will receive a copy of the seminar materials and Lattice Diamond™ design software in a convenient DVD format. Dates and locations will be published on the Lattice Semiconductor website, www.latticesemi.com. Contact your local Lattice Sales Representative for more information.

About the MachXO2 PLD Family
The MachXO2 devices provide designers of low density PLDs an unprecedented mix of low cost, low power and high system integration in a single device. Built on a low power 65-nm process featuring embedded Flash technology, the MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory, more than a 100X reduction in static power to as low as 19uW and up to 30% lower cost compared to the prior generation MachXO™ PLD family. These devices are ideal for control PLD applications in end markets such as telecom infrastructure, computing, high end industrial, high end medical, and low power applications such as smart phones, GPS devices and digital cameras.

About the LatticeECP3 FPGA Family
The award-winning LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs.

About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com.
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Lattice Semiconductor Corporation, Lattice (& design), L (& design), Lattice Diamond, LatticeECP3, MachXO2, MachXO and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Contact Information

  • EDITORIAL/READER CONTACT:
    Brian Kiernan
    Corporate Communications Manager
    Lattice Semiconductor Corporation
    503-268-8739 voice
    503-268-8193 fax
    brian.kiernan@latticesemi.com