SOURCE: Real Intent

April 03, 2007 14:32 ET

Real Intent Releases Next Generation Timing Exception Verifier

PureTime 2.0 Adds SDC Exception Linting, the Ability to Verify Clock Domain Crossing Exceptions, and Improves Performance

SUNNYVALE, CA -- (MARKET WIRE) -- April 3, 2007 -- Real Intent, Inc., the leading supplier of formal verification software for electronic design, announced that the next generation of its formal timing exception verifier software, PureTime 2.0, is shipping.

PureTime removes the risk of errors in Synopsys Design Constraint (SDC) timing exception verification, so that designers can avoid chip respins and electronic product introduction delays. Its automatic timing exception processing dramatically improves project schedules when compared to a manual review of timing exceptions.

"Our customers are constantly looking for ways to improve the ROI of their engineering staff and tools expenditures. Verifying hundreds of lines of SDC through manual design review is error prone, extremely time consuming, and is expensive in terms of engineering time and delays to product shipments," said Rich Faris, Vice President of Marketing and Business Development at Real Intent. "Moreover, an automatic solution is accurate, whereas manual reviews are more error prone."

What's New

PureTime 2.0 extends Real Intent's leadership position in exception verification by adding comprehensive SDC exception linting capability and the ability to verify clock domain crossing exceptions. More capabilities new with 2.0 include the automatic export of expanded SDC, support for wildcarding in the SDC file, and enhanced algorithms for higher performance.

Sequential vs. Combinatorial Analysis

PureTime 2.0 offers full sequential analysis and multi-cycle path analysis. Combinatorial only solutions can invalidate paths that full sequential analysis correctly identifies as valid, and can't analyze multi-cycle paths.

About PureTime

PureTime is a software timing exception verifier that detects timing exception errors that create schedule delays, chip respins or failing hardware. Using exhaustive formal analysis, it proves the correctness of SDC false-path and multi-cycle path exceptions. These exceptions can be created by designers, received as a part of Intellectual Property (IP), or generated by other tools. PureTime works throughout the entire design flow, with both RTL and netlist designs. It includes comprehensive exception linting capabilities, and is glitch and interaction aware for highest accuracy.

About Real Intent

Real Intent is extending breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent's products dramatically improve the functional verification efficiency of leading edge application specific integrated circuit (ASIC), system-on-chip (SOC), and Field Programmable Gate Array (FPGA) devices. Over 40 major electronics design houses, including Sun Microsystems, AMD, Marvell Technology Group, nVidia, and NEC Electronics use Real Intent software.

Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: (408) 830-0700 fax: (408) 737-1962, web:, e-mail:

Notes to editors:

Graphics and/or screen shots available on request.
PureTime is a trademark of Real Intent Inc.
All other trademarks or registered trademarks are property of their
respective owners.

Contact Information

  • Press contacts:
    Rich Faris
    Real Intent Vice President Marketing and Business Development
    (408) 830-0700 x212
    Email Contact

    Georgia Marszalek
    Valley PR for Real Intent
    (650) 345-7477
    Email Contact