SOURCE: Accellera

December 15, 2008 15:00 ET

Reminder - Accellera Announces Call for Nominations for 2009 Annual Technical Excellence Award Honoring Contributions to Electronic Design Automation Standards

Nominations Are Due Friday, January 9, 2009

NAPA, CA--(Marketwire - December 15, 2008) -


Accellera, the electronics industry organization focused on Electronic Design Automation (EDA) standards, invites the electronic design community to nominate an individual for its 6th annual Technical Excellence Award. Accellera's Technical Excellence Award recognizes the outstanding achievements of its Technical Subcommittee members in creating electronic design standards that benefit the EDA, semiconductor, intellectual property (IP) and electronic systems industries.

Accellera provides a framework that enables the technical work of its committees, logistics and the infrastructure for obtaining and distributing funds and resources for EDA standards, that when approved are available to everyone in the electronics community at no cost.


Accellera's Technical Excellence Award nominations are due Friday, January 9, 2009. Accellera's Technical Excellence Award will be presented during Accellera's Design Verification Conference (DVCon), February 24-26, 2009, at the Doubletree Hotel in San Jose.


For more information about Accellera and its EDA standards please visit To nominate an individual, please visit For more information about DVCon, please visit

About Accellera's Technical Subcommittees

Accellera's Technical Subcommittees produce effective and efficient standards for today's advanced IC designs. Participation comes from Accellera member companies, industry contributors, and independents. Technical contributors typically have many years of practical experience with IC design and developing and using design automation tools.

Accellera's Technical Subcommittees include: Interface (ITC), Open Compression Interface (OCI), Open Verification Language (OVL), Property Specification Standard (PSL), SystemVerilog, Unified Coverage Interoperability (UCI), Unified Power Format (UPF), Verilog Analog/Mixed-Signal (Verilog-AMS), Verification Intellectual Property (VIP) and VHDL. More information is at

About Accellera's IEEE Electronic Design Standards

Accellera has transferred its completed standards work to the IEEE and continues to use this strategy as part of the roadmap for all of its standards.

To date, seven Accellera EDA standards have been ratified by the IEEE -- Hardware Description Language (HDL) standards, Verilog or IEEE 1364, VHDL or IEEE1076, Property Specification Language (PSL) or IEEE 1850 and SystemVerilog or IEEE 1800; Standard Delay Format (SDF) or IEEE 1497; Delay and Power Calculation System (DPCS) or IEEE 1481 and Advanced Library Format (ALF) or IEEE 1603. In addition, two standards are active in IEEE Working Groups, Open Compression Interface (OCI) or IEEE 1718 and Unified Power Format (UPF) or IEEE P1801. Accellera's most recent advanced design and verification language standards include the SystemVerilog and the PSL standards.

About Accellera

Accellera provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are provided to the IEEE Standards Association for formalization and ongoing change control. For more information about Accellera, please visit

Notes to Editors:

Acronyms and Abbreviations
ALF   Advanced Library Format
AMS   Analog, Mixed Signal
DPCS  Delay and Power Calculation System
EDA   Electronic Design Automation
HDL   Hardware Description Language
IC    Integrated Circuit
IEEE  Institute of Electrical and Electronics Engineers
OCI   Open Compression Interface
PSL   Property Specification Language
SDF   Standard Delay Format
Std.  Standard
UPF   Unified Power Format
VHDL  Very High-Speed IC (VHSIC) HDL

All trademarks and tradenames are the property of their respective owners.

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