SOURCE: Carbon Design Systems

April 16, 2007 01:00 ET

Reminder - Carbon Design Systems Exhibits at DATE 2007 and Hosts Luncheon Seminar on Concurrent Hardware-Software Design and Debugging

Carbon's Stand M30, April 17-19, Acropolis, Nice, France

NICE, FRANCE -- (MARKET WIRE) -- April 16, 2007 --


Who/What:

Carbon Design Systems is the leading supplier of system-level tools for the creation, validation and deployment of fast cycle-accurate hardware models automatically generated from RTL descriptions. Carbon will be hosting a luncheon seminar and exhibiting at the Design Automation and Test (DATE) 2007 Conference. The free seminar will describe a virtual platform for concurrent hardware and software design and debugging. Demonstrations at the Carbon exhibit will show how a system's architecture can be optimized and the accompanying software validated months before silicon implementation.

When/Where:

Concurrent Design and Debug Seminar with Lunch
Tuesday, 17th April, starts at noon
Gallieni 4, Acropolis, Nice, France
Exhibit
Tuesday, 17th April, 10:00 am-7:00 pm
Wednesday, 18th April, 10:00 am-6:00 pm
Thursday, 19th April, 10:00 am-5:00 pm
Booth #M30, Mediterranee Floor
Acropolis, Nice, France
Information and Appointments:

For more information about DATE, please visit www.date-conference.com

To register for the seminar, please go to: http://www.carbondesignsystems.com/corpsite/products/webinars/seminar.html

To make an appointment with Carbon, please email deb@carbondesignsystems.com.

Carbon's SOC-VSP™ Software

Verilog and/or VHDL are compiled by SOC-VSP software into high-performance hardware models with transaction-level interfaces added from Carbon's extensive library. These models can be simulated as part of a system-level simulation using popular platforms from ARM, CoWare, MIPS, and the Open SystemC Initiative (OSCI). Carbon's models enable system architects to profile performance and explore software-hardware boundaries with cycle accuracy. Architectural deficiencies can be discovered and fixed early in the design cycle. Hardware engineers can debug their designs with 100% visibility and dump waveforms in either VCD or FSDB formats. Firmware engineers can quickly iterate through their code with Carbon's new Replay™ technology, set hardware breakpoints, and peek or poke registers with Carbon's intuitive interface.

About Carbon:

The company is headquartered at 375 Totten Pond Road, Suite 100/200, Waltham, MA. 02451. Telephone: 781.890.1500, Fax: 781.890.1711, Email: info@CarbonDesignSystems.com, Websites: www.carbondesignsystems.com and www.easypass2esl.com.

Carbon Design Systems, SOC-VSP, and Replay are trademarks of Carbon Design Systems, Incorporated. SystemC is a trademark of the Open SystemC Initiative. All other companies and products referenced herein are trademarks or registered trademarks of their respective holders.

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