SOURCE: Accellera

Accellera

June 14, 2010 06:00 ET

REMINDER: Celebrate Accellera's 10 Years of Standards Excellence at 47th DAC

Attend Universal Verification Methodology (UVM) Breakfast Panel and Low Power Tutorial, Learn About EDA and IP Standards

ANAHEIM, CA--(Marketwire - June 14, 2010) -


Who/What
At the 47th Design Automation Conference (DAC), Accellera invites the electronic design community to attend its breakfast and learn more about its Electronic Design Automation (EDA) and Intellectual Property (IP) standards.

Accellera's DAC breakfast, sponsored by Cadence, Mentor and Synopsys, will feature a standards update with an overview of how the Universal Verification Methodology (UVM) standard supports verification tool interoperability and gives IP and EDA users more choices, and a panel on "UVM: Charting the New Territory." This event continues the celebration of Accellera's 10 years of standards excellence.

As part of the DAC Tutorials, experts will present on "Low Power from A to Z." This tutorial will cover Accellera Unified Power Format (UPF) standard, also known as IEEE 1801.

The Synopsys Standards Booth will showcase SystemVerilog (also known as IEEE Std.1800) verification-based interoperability and Accellera's UVM Base Class library. At Synopsys Conversation Central, Accellera's chair, Mr. Shrenik Mehta, will speak about Accellera's role in industry standards. Accellera's Verification Intellectual Property Technical Subcommittee (VIP-TSC) co-chairs, Mr. Thomas Alsop and Mr. Hillel Miller, will also talk about UVM at the Open Verification Methodology (OVM) World booth and at Synopsys' Conversation Central.

About Accellera's Breakfast Panel:

Title: "UVM: Charting the New Territory"
Abstract: Accellera's VIP-TSC has been actively working on UVM and its Early Adopter release. Current features of UVM can be best described as the reflection of verification methodology in use by the industry. Listen to a panel of expert verification engineers and methodology developers debate what they would like to see in UVM by DAC 2011. Is it more of the same, some incremental stuff, radical new technologies, or keep-it-as-is status quo for you? This is the time to find out more, and even chime in with your own views.
Panelists: Sharon Rosenberg, Cadence Design Systems
Hillel Miller, Freescale
Mohamed Elmalaki, Intel Corp.
Tom Fitzpatrick, Mentor
Janick Bergeron, Synopsys, Inc.
Stacey Secatch, Xilinx
Moderator: Gabe Moretti, GabeOnEDA

About the DAC Low Power Tutorial
Title: "Low Power from A to Z"
Summary: This tutorial is aimed at providing a comprehensive look at how low power design permeates all levels of the design process. It will cover UPF and case studies.
Organizer: Dennis Sylvester, Univ. of Michigan, Ann Arbor, MI
Speakers: Robert Aitken, ARM Ltd.
Vivek Chickermane, Cadence Design Systems
Steve Curtis, Intel Corp.
Godwin Maben, Synopsys, Inc.
Srinivasa R. Sridhara, Texas Instruments, Inc.

When/ Where
Tutorial: "Low Power from A to Z"
9:00am - 5:00pm, Monday, June 14, 2010
Anaheim Convention Center 210CD

Accellera Breakfast and Panel
7:30am - 9:00am, Tuesday, June 15, 2010
Anaheim Convention Center, Room 203B

Accellera Standards Discussions
Tuesday, June 15, 2010
1:30pm - 2:00pm, UVM
3:30pm - 4:00pm Accellera standards
Synopsys Conversation Central at Booth #595

Accellera UVM Talk
11:00am - 11:30am, Monday, June 14, 2010
OVM World, Booth #1350

SystemVerilog and Accellera UVM
9:00am - 6:00pm, Monday, June 14 - Wednesday, June 16, 2010
Synopsys Standards Booth # 585

Anaheim Convention Center, Anaheim, California

Information
To register for the Accellera's DAC breakfast, please visit http://www.accellera.org/events/.
For more information about Accellera, please visit www.accellera.org.
For more information about DAC, please visit www.dac.com.

About Accellera
Accellera, an industry organization formed in 2000, provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are transferred to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org. For membership information, please email membership@accellera.org.

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Contact Information

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