SOURCE: Real Intent

February 19, 2008 15:00 ET

Reminder - Clock Domain Crossing and Bug Hunting Software Take Center Stage at Real Intent's DVCon Exhibit, Program Features Tutorial by Cliff Cummings and Rich Faris on Design and Verification of Asynchronous Clock Crossings in a SystemVerilog World

SAN JOSE, CA--(Marketwire - February 19, 2008) -


Who/What:

Real Intent, Inc., the leading supplier of formal verification software for electronic design, will demonstrate its proven Clock Domain Crossing (CDC) verification and Bug Hunting formal verification software at DVCon, the premier conference for functional design and verification of digital electronic systems.

Cliff Cummings of Sunburst Design and Rich Faris of Real Intent are featured as part of the conference's Tutorial program and will present on "Design and Verification of Asynchronous Clock Crossings in a SystemVerilog World."

When/Where:

Exhibits and Demonstrations:
Tuesday, February 19, 2008 -- 4:30pm - 7:30pm (Bayshore Ballroom)
Wednesday, February 20, 2008 -- 4:30pm - 7:30pm (Bayshore Ballroom)

Tutorial:
Thursday, February 21, 2008 -- 3:30pm-5:00pm (Donner Ballroom)
DoubleTree Hotel San Jose, 2050 Gateway Place, San Jose, CA 95110

Information

For more information about DVCon, please visit www.DVcon.com.

For more information about Real Intent, please visit www.realintent.com.

Real Intent's EnVision™ Family includes:

Ascent™, an automatic bug hunting tool that can run even before simulation on Register Transfer Level (RTL) designs, requires no testbench, and supports both the Property Specification Language (PSL) and SystemVerilog Assertions (SVA) constraints;

Conquest™, an Assertion-Based Verification (ABV) tool with engines that excels in capacity and performance when compared to competing products;

Meridian CDC, a checker for the integrity of signals crossing clock domains; which includes the most comprehensive 3 strategies in industry, including Structural, Dynamic, and Formal. and

PureTime™, automatic software for verifying timing exception constraints such as Synopsys Design Constraints for set_false_path and set_multicycle_path commands.

About Real Intent

Real Intent extends breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent's products dramatically improve the functional verification efficiency of leading edge Application Specific Integrated Circuit (ASIC), System-On-Chip (SOC), and Field Programmable Gate Array (FPGA) devices. Over 40 major electronics design houses, including AMD, nVidia and NEC Electronics, use Real Intent software.

Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: (408) 830-0700 fax: (408) 737-1962, web: www.realintent.com, e-mail: info@realintent.com.

EnVision, Conquest, Ascent, and PureTime are trademarks of Real Intent, Inc. All other trademarks or registered trademarks are property of their respective owners.

Contact Information