January 23, 2007 14:28 ET

Renesas Adopts Cadence Encounter RTL Compiler for ASIC Designs at 90 NM and Below

Advanced Global Synthesis Technology Enables Renesas and Its ASIC Customers to Achieve Timing, Area and Power-Consumption Advantages

SAN JOSE, CA -- (MARKET WIRE) -- January 23, 2007 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Renesas Technology Corp. has adopted Cadence® Encounter® RTL Compiler with advanced global synthesis, a key technology of the Encounter digital IC design platform, in its ASIC design kits and methodologies for 90 nanometers and below. Renesas is extending their current ASIC kits and methodologies to add support for Encounter RTL Compiler.

Renesas, one of the world's leading semiconductor-solutions providers for the mobile, automotive and PC/AV (Audio Visual) markets, successfully evaluated Encounter RTL Compiler on large high-performance ASIC blocks. The resulting blocks achieved greater timing improvement and reduction in area over previously used methodologies. Renesas has also successfully applied Encounter RTL Compiler's advanced clock-gating optimization to enable dynamic power reduction and simpler clock-tree.

"Our evaluation of Cadence Encounter RTL Compiler for synthesis of ASIC designs has shown us its value in creating optimized netlists for large and complex designs," said Teruaki Harada, department manager, DFM and EDA Technology Development at Design Technology Division, Renesas. "We have adopted Encounter RTL Compiler for future tapeouts and will now support it for our external ASIC customers."

Encounter RTL Compiler with global synthesis has proven through tapeouts to deliver improved performance, smaller die sizes, lower power consumption, and faster design closure through place and route. This ability to produce smaller, faster and cooler chips in less time has increased customer competitiveness and reduced overall costs. Encounter RTL Compiler is available in L, XL and GXL configurations.

"We are pleased that, with the adoption of Encounter RTL Compiler, Renesas is able to achieve design success with large, high-performance ASIC chips," said Nimish Modi, corporate vice president, R&D at Cadence. "Encounter RTL Compiler with global synthesis is a production-proven tool that delivers real business benefits for ASIC customers."

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence and Encounter are registered trademarks, and, the Cadence logo is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Contact Information

  • For more information, please contact:
    Michael Fournell
    Cadence Design Systems, Inc.