February 09, 2006 12:00 ET

SEMATECH Launches 3D Project to Probe Options for Advanced Interconnect

AUSTIN, TX -- (MARKET WIRE) -- February 9, 2006 -- Aiming to expand the range of potential solutions to the challenges of continued CMOS scaling, SEMATECH has launched a project to explore the feasibility of three-dimensional (3D) interconnect technology for the semiconductor industry.

The SEMATECH effort will develop a cost model for 3D migration and create a prioritized list of industry 3D infrastructure needs for the consortium's member companies, while also working to develop industry consensus on standards needed for 3D technology. At the appropriate times, these activities will be expanded to prove the feasibility of the technology in the areas of materials, unit processes, integration, and reliability.

"The criteria for analysis will, of course, be cost effectiveness and functionality/performance enhancement," said Sitaram Arkalgud, director of SEMATECH's Interconnect Division. He added that 3D may emerge as the industry's best option in meeting the interconnect goals of the International Technology Roadmap for Semiconductors (ITRS).

"The industry has been pursuing copper and low-k interconnect technology since the mid-1990s, and true low-k materials are beginning to move into real products," Arkalgud noted. "However, decreasing k-effective by constantly changing dielectrics, and often the assist layers, presents challenges -- notably with developing and requalifying new metals continuously."

Arkalgud continued: "The ITRS shows that low-k technology alone will not be sufficient to meet the needs of microdevices in 2010. Of the available options, 3D may offer the least disruptive path to the next interconnect paradigm."

3D interconnect involves the physical and electrical bonding of semiconductor wafers and dies, using deep through-silicon vias, to produce multilevel microchips with advanced processing capabilities. If proven feasible for volume manufacturing, 3D could provide a path toward integrating chips that are more cost-effective and easier to engineer. "A validated cost model that clearly shows the economic benefits of 3D will be key to the acceptance of this technology by the industry," Arkalgud said.

Arkalgud said the 3D project augments SEMATECH's low-k development program, which will emphasize chemical vapor deposition (CVD) films.

Meanwhile, initial 3D project work has begun with formation of a working group of about 20 SEMATECH member company representatives, who will assess the key challenges of 3D and the available options for addressing them. The group will strive to develop a 3D roadmap for members, with the ultimate goal of transferring its roadmapping process to the ITRS.

"Our program will focus on wafer-on-wafer and die-on-wafer structures," Arkalgud said. "Solutions will be sought for both high-performance and low-cost products." Interconnect engineers will utilize the cost model and work with representatives of the microchip industry to develop consensus on key industry-wide issues, he added.

"SEMATECH's well-established ability to do benchmarking will bring added resources to this effort, and we'll leverage our other projects to help achieve these goals," Arkalgud said.

SEMATECH is the world's catalyst for accelerating the commercialization of technology innovations into manufacturing solutions. By setting global direction, creating opportunities for flexible collaboration, and conducting strategic R&D, SEMATECH delivers significant leverage to our semiconductor and emerging technology partners. In short, we are accelerating the next technology revolution. For more information, please visit our website at SEMATECH, the SEMATECH logo, AMRC, Advanced Materials Research Center, ATDF, the ATDF logo, Advanced Technology Development Facility, ISMI and International SEMATECH Manufacturing Initiative are servicemarks of SEMATECH, Inc.

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