SOURCE: SEMATECH

March 08, 2006 12:00 ET

SEMATECH to Investigate Alternate Channel Materials for Advanced Microchips

AUSTIN, TX -- (MARKET WIRE) -- March 8, 2006 -- Pushed by the scaling limits of silicon-based devices, SEMATECH engineers have launched a project to investigate alternative materials to Si in MOSFET channels, the critical pathways that allow electrical signals to flow across transistors.

The project in SEMATECH's Front End Processes (FEP) division will focus on the applicability of silicon-germanium and germanium as channel materials, with attention to developing process technology that will help realize the promise of enhanced mobility without compromised reliability.

"Silicon-germanium and germanium are currently the most promising materials for replacing silicon in planar channels in CMOS manufacturing," said Larry Larson, FEP associate director. "Our development direction is to explore the compatibility of these materials with SEMATECH's world-class gate stack materials systems, and develop new solutions where needed."

"As a channel material for current geometries, silicon is still the best; in many ways, it's been nature's gift to electrical engineers," said Hsing-Huang Tseng, a Freescale assignee and manager of FEP's new CMOS Extension Program. "But continued CMOS scaling means we need to find new materials to replace silicon in these functions. Germanium and silicon-germanium, and potentially III-V compounds in the longer term, could provide even bigger benefits for mobility enhancement."

SEMATECH launched the alternative materials effort in December 2005 by hosting an international industry workshop in Washington, D.C. Meeting participants, including experts from SEMATECH member companies and key research universities, were asked to narrow down the list of potential replacement materials and technical challenges.

"The workshop identified four or five material combinations and these were referred to participating universities for long-term work," said Tseng. Meanwhile, SEMATECH is targeting Si-Ge and Ge for development for use in volume manufacturing.

Sharing several elemental properties with silicon, Ge once rivaled Si as a basic semiconductor material, but was largely discarded because of difficult integration issues. The chip industry's renewed interest in Ge as a cutting-edge material involves some delving into historical sources to learn its capabilities. "We're going back to publications from 1954 to obtain basic information on germanium," Larson acknowledged.

Raj Jammy, SEMATECH's FEP director, added: "Our goal is not to replace silicon entirely, but to apply higher-mobility channel materials selectively on tried and trusted silicon-based technology for continued CMOS scaling. This will require not only developing processing techniques to put down alternate channel materials on silicon with low defect densities, but also to develop techniques to form compatible source-drain junctions and gate stacks."

Jammy added that SEMATECH's entry into Si-Ge/Ge is aimed at developing manufacturable solutions for members by screening materials and process options. Also, SEMATECH's alternate-materials projects will be cross-linked with strategic efforts on suitable gate stack and source-drain junction development as well as corollary programs with tool suppliers.

"The need for solutions with alternate channel materials and other high performance materials options has become critically important as we finally encounter the limits of silicon," Jammy explained. "Now that silicon device dimensions are approaching practical physical limits and involve increasingly complex processing techniques, alternate channels are becoming an attractive option for the first time."

FEP engineers will combine such research with data and methods from FEP's successful projects in high-mobility, high-k materials and dual metal gate stacks to assess the current suitability of Si-Ge and Ge for channels. Initial work will focus on areas such as:

     Evaluating the most promising variations of Si-Ge for low defect
      density and performance enhancement

     Developing and characterizing the performance of Si-Ge and Ge
      source and drain junctions

     Finding a suitable interface between a Ge-based channel and a
      high-k dielectric material in an advanced gate stack
"This project is a major new effort for SEMATECH, with potentially far-reaching implications for the industry," noted Larson. "We hope to identify the most manufacturable solutions for our members, who are seeking ways to boost performance and continue CMOS scaling."

SEMATECH is a global semiconductor technology development consortium that has effectively represented the semiconductor manufacturing industry on innovation issues since 1988. SEMATECH conducts state-of-the-art research, and is a highly regarded technology partner whose goal is to promote the interests common to all chipmakers. It has extensive experience collaborating with equipment and materials suppliers, as well as government and academic research centers, to refine the tools and technology necessary to produce future generations of chips. Additional information may be found at www.sematech.org. SEMATECH, the SEMATECH logo, AMRC, Advanced Materials Research Center, ATDF, the ATDF logo, Advanced Technology Development Facility, ISMI and International SEMATECH Manufacturing Initiative are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

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