SOURCE: Sidense

Sidense

October 10, 2012 09:00 ET

Sidense Exhibiting and Presenting at TSMC Open Innovation Platform (OIP) Ecosystem Forum

Presentation Will Discuss the Use of 1T-OTP in Mobile and Other Low-Power Applications

OTTAWA and SANTA CLARA, CA--(Marketwire - Oct 10, 2012) -

What
Sidense exhibiting and speaking at the TSMC OIP Forum

Where
San Jose Convention Center
150 West San Carlos Street
San Jose, CA 95110
Booth #503

When
Tuesday, October 16
8:00AM to 6:00PM

Sidense to present at 11:30AM:
1T-OTP - Non-Volatile Memory for Mobile and Other Low-Power Applications

About Sidense
Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required. The Company's innovative one-transistor 1T-Fuse™ architecture provides the industry's smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (LNVM) IP solution. With over 100 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.

Sidense SiPROM, SLP and ULP memory products, embedded in more than 240 customer designs, are available from 180nm down to 28nm and are scalable to 20nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic. For more information, please visit www.sidense.com.

About the OIP Forum
The TSMC Open Innovation Platform® (OIP) Ecosystem Forum brings TSMC's design ecosystem member companies together to share with our customers real-case solutions for customers' design challenges and success stories of best practice in TSMC's design ecosystem.

This year, the forum will feature a day-long conference starting with executive keynotes from TSMC and ARM in the morning plenary session to outline future design challenges and roadmaps, as well as discuss a recent collaboration announcement; 30 selected technical papers from TSMC's EDA, IP, Design Center Alliance and Value Chain Aggregator member companies; and an Ecosystem Pavilion featuring member companies showcasing their products and services.

Contact Information

  • For more information or to schedule a meeting with Sidense, please contact:

    Jim Lipman
    Sidense
    Email Contact
    925-606-1370