SOURCE: Silistix

March 05, 2007 11:00 ET

Silistix/Intel Co-Authored Paper to Be Presented at ASYNC 2007

Paper Discusses Asynchronous Interconnect Exploration on the Intel PXA27x Processor Peripheral Bus

SAN JOSE, CA -- (MARKET WIRE) -- March 5, 2007 --


ASYNC 2007, University of California at Berkeley, Berkeley, California


Monday, March 12, 1:30-3:00PM
Technical Session 2: Asynchronous Applications

The paper examines the use of GALS (Globally Asynchronous, Locally Synchronous) techniques to address on-chip communication between different synchronous modules on a bus. The authors explore issues related to validation, module interfaces, and tool flows while looking at advantages in power savings, timing closure, and Time-to-Market/Time-to-Money (TTM).

To arrange a meeting with Silistix CEO David Fritz after the paper presentation to discuss Silistix's work on self-timed SoC interconnect, please contact:

Jim Lipman
Cain Communications
About Silistix

Silistix is a venture-funded spin-out of the University of Manchester, UK, with backing from Intel Capital. The company's focus is on the development and deployment of EDA tools for the design and synthesis of self-timed CHAIN technology for complex system-on-a-chip (SoC) communication. The company has offices in Manchester, England, San Jose, California, and Tokyo, Japan. For more information call 408-878-6098 or visit

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