SOURCE: STATS ChipPAC

STATS ChipPAC

July 08, 2012 19:30 ET

STATS ChipPAC Announces Volume Manufacturing of fcCuBE™ Technology and Expanded Processing Capability for This Advanced Flip Chip Packaging Solution

Flexibility to Support Both Conventional Mass Reflow and Thermo-Compression Bond Processing Addresses a Wider Range of Copper Bump Pitches and Market Applications

SINGAPORE--09/07/2012, UNITED STATES--(Marketwire - Jul 8, 2012) - STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company") (SGX-ST: STATSChP), a leading semiconductor test and advanced packaging service provider, today announced its innovative fcCuBE™ technology, an advanced flip chip packaging technology that features copper (Cu) column bumps, Bond-on-Lead (BOL) interconnection and Enhanced assembly processes, is in high volume production for multiple customers and the Company has expanded its assembly processing capabilities to address a wider spectrum of bump pitch ranges from > 200 micron (um) to below 80um. 

fcCuBE technology was designed to significantly reduce the cost of flip chip packaging, expand the scalability of flip chip technology to much finer bump pitches and higher input/output (I/O) densities, and eliminate stress on the delicate ELK/ULK structures at advanced silicon wafer nodes. With STATS ChipPAC's patented BOL interconnect structure in combination with Cu column bumps, fcCuBE technology has shown to effectively address each of these objectives in a growing number customer applications. 

A unique feature of fcCuBE technology is the ability to support both a standard mass reflow assembly process or a Thermo-Compression Bonding (TCB) process. With mass reflow, STATS ChipPAC has been able to achieve a 10-30% cost reduction in package designs with fcCuBE technology as compared to conventional flip chip interconnect. STATS ChipPAC has qualified fcCuBE down to 80um bump pitch using mass reflow and is in development of finer pitches.

"fcCuBE technology with the mass reflow assembly option has provided our customers with the benefit of having an advanced flip chip package with increased device performance and superior reliability at a price point comparable to mainstream semiconductor packages. We are in volume production with multiple customers and continue to engage this technology in a wide range of products and applications. With the inherent scalability of fcCuBE, we have expanded our services to provide customers with a Thermo-Compression Bonding assembly process which supports ultra-high densities at advanced silicon nodes and emerging 3D technology such as Through Silicon Via (TSV) interconnection," said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.

TCB is a more complex interconnect process as compared to mass reflow, providing the increased level of precision required for bonding higher density and tighter pitch flip chip configurations. For fine pitch bump requirements, TCB enables the assembly of very small bump diameters in more advanced wafer fab nodes and supports bonding requirements such as chip-to-substrate or chip-to-chip. This provides STATS ChipPAC's customers with the flexibility to select either the mass reflow or TCB assembly process with fcCuBE technology and allows a more optimized package design across the widest range of bump pitches, particularly with a co-design relationship.

Dr. Han continued, "By expanding the capabilities of our fcCuBE technology, we can provide our customers with a new and unique degree of flexibility in choosing the process that best meets the cost and performance requirements of their specific application. The wide range of bump pitches and I/O density covered by mass reflow addresses a large majority of the flip chip package designs down through the 20nm silicon wafer node. For customers with finer pitch, higher density requirements, we now have TCB."

Forward-Looking Statements
Certain statements in this release are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, the timing and impact of the expected closure of the Thailand Plant as well as the estimated associated cost for the closure; the amount of the property damage and business interruption insurance claim due to flooding of the Thailand Plant; the ability to shift production to other manufacturing locations, shortages in supply of key components and disruption in supply chain; general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilisation; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; customer credit risks; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; classification of our Company as a passive foreign investment company; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited ("Temasek") that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labour union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; the continued trading and listing of our ordinary shares on the Singapore Exchange Securities Trading Limited ("SGX-ST"). You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.

About STATS ChipPAC Ltd.
STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices in 10 different countries. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.

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